Overview Of I/O Memory Area; I/O Memory Area - Omron CP1L CPU UNIT - 06-2007 Operation Manual

Overview of I/O Memory Area

4-1 Overview of I/O Memory Area
4-1-1

I/O Memory Area

Area
CIO I/O Area Input 1,600 bits
Area Area (100
words)
Output 1,600 bits
Area (100
words)
1:1 Link Area 1,024 bits
(64 words)
Serial PLC Link Area 1,440 bits
(90 words)
Work Area 14,400
bits (900
words)
Work Area 8,192 bits
(512
words)
Holding Area 8,192 bits
(512
words)
Auxiliary Area 15,360
bits (960
words)
TR Area 16 bits
Data Memory Area 32,768
words
Timer Completion Flags 4,096 bits
Counter Completion Flags 4,096 bits
Timer PVs 4,096
words
Counter PVs 4,096
words
Task Flag Area 32 bits
Index Registers 16 regis-
ters
Data Registers 16 regis-
ters
122
This region of memory contains the data areas that can be accessed as
instruction operands. I/O memory includes the CIO Area, Work Area, Holding
Area, Auxiliary Area, DM Area, Timer Area, Counter Area, Task Flag Area,
Data Registers, Index Registers, Condition Flag Area, and Clock Pulse Area.
Size Range Task usage
CIO 0 to Shared by
CIO 99 all tasks
CIO 100
to CIO
199
CIO 3000
to CIO
3063
CIO 3100
to CIO
3189
CIO 3800
to CIO
6143
W000 to
W511
H000 to
H511
(Note 6)
A000 to
A959
TR0 to
TR15
D00000
to
D32767
(Note 7)
T0000 to
T4095
C0000 to
C4095
T0000 to
T4095
C0000 to
C4095
TK0 to
TK31
IR0 to Function
IR15 separately in
each task
(Note 3)
DR0 to
DR15
Note 1. A0 to A447 are read only and cannot be written. A448 to A959 are
read/write.
2. Bits can be manipulated using TST(350), TSTN(351), SET, SETB(532),
RSTB(533), and OUTB(534).
Instruction
Allocation Bit Word
access access
CP1L CPU OK OK
Units and CP-
series Expan-
sion Units or
OK OK
Expansion I/O
Units
1:1 Links OK OK
Serial PLC OK OK
Links
--- OK OK
--- OK OK
--- OK OK
--- OK ---
--- OK OK
--- No OK
(Note
2)
--- OK ---
--- OK ---
--- --- OK
--- --- OK
--- OK ---
--- OK OK
--- No OK
Section 4-1
I/O Memory
Access Change
from CX-
Read Write
Programmer
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK Note 1 Note 1
OK OK No
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK No No
Indirect Specific No
address- instruc-
ing only tions only
OK OK No
Forcing
bit
status
OK
OK
OK
OK
OK
OK
OK
No
No
No
OK
OK
No
(Note 4)
No
(Note 5)
No
No
No