Omron CP1L CPU UNIT - 06-2007 Operation Manual page 80

Specifications
Address Input operation settings
Word Bit Normal
inputs
CIO 1 00 Normal
input 12
01 Normal
input 13
02 Normal
input 14
03 Normal
input 15
04 Normal
input 16
05 Normal
input 17
06 Normal
input 18
07 Normal
input 19
08 Normal
input 20
09 Normal
input 21
10 Normal
input 22
11 Normal
input 23
Output Terminal Block Arrangement (Bottom Block)
AC Power Supply Models
+
−
DC Power Supply Models
NC
NC
Interrupt Quick-
inputs response
(See note.) inputs
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00 01 02 03
COM
COM
COM COM
CIO 100
00 01 02 03
COM
COM
COM COM
CIO 100
High-speed counters
Operation settings:
High-speed counters enabled
Phase-Z reset
Single-phase Two-phase (differential
(increment phase x4, up/down, or
pulse input) pulse/direction)
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04 06
00 01
COM 02
05
07
CIO 101
04 06
00 01
COM 02
05
07
CIO 101
Section 2-2
Origin searches
Origin searches
enabled for pulse
outputs 0 and 1
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03 04 06
COM 07
05
03 04 06
COM 07
05
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