Omron CP1L CPU UNIT - 06-2007 Operation Manual page 88

Specifications
Item
High-speed Counter Inputs
2.5 µs max.
OFF delay
Circuit configuration
Note
High-speed Counter Inputs
CIO 0.00 to CIO 0.03
Input bits: CIO 0.04 to CIO 0.11
IN
IN
COM
Input bits: CIO 0.00 to CIO 0.03, CIO 1.00 to CIO 1.03
IN
IN
COM
Input bits: CIO 1.04 to CIO 1.11
IN
IN
COM
(1) HIgh-speed counter inputs, interrupt inputs, and quick-response inputs
can also be used as normal inputs.
(2) The bits that can be used depend on the model of CPU Unit.
(3) The response time is the hardware delay value. The delay set in the PLC
Setup (0 to 32 ms, default: 8 ms) must be added to this value.
Bit Differential
phase mode
CIO 0.00, A-phase pulse
CIO 0.02 input
CIO 0.01, B-phase pulse
CIO 0.03 input
CIO 0.04, Z-phase pulse input or hardware reset input (Can be used as ordinary
CIO 0.05 inputs when high-speed counter is not being used.)
Max. count 50 kHz (4×)
frequency
Specification
Interrupt Inputs and
Quick-response Inputs
CIO 0.04 to CIO 0.09 (See
note 1.)
50 µs max.
Input LED
1000 pF
Internal
3.0 kΩ
circuits
Input LED
1000 pF
Internal
3.0 kΩ
circuits
Input LED
Internal
4.7 kΩ
circuits
Pulse plus
direction input
mode
Pulse input
Direction input
100 kHz
Section 2-2
Normal inputs
CIO 0.10 to CIO 0.11 and
CIO 1.00 to 1.11 (See note 2.)
1 ms max. (See note 3.)
Up/down input Increment
mode mode
Increment pulse Increment pulse
input input
Decrement Normal input
pulse input
55