Ac97 Bit Timing Near Frame Synchronization - Texas Instruments TMS320C6000 Reference Manual

Figure 16.

AC97 Bit Timing Near Frame Synchronization

CLKR
FSR
DR P2E12B1
Legend: PxEyBz = phase x, element y, and bit z.
SPRU580C
Figure 15 shows the AC97 timing near frame synchronization. First the frame
sync pulse itself overlaps the first element. In McBSP operation, the
inactive-to-active transition of the frame synchronization signal actually
indicates frame synchronization. For this reason, frame synchronization can
be high for an arbitrary number of bit clocks. Only after the frame
synchronization is recognized as inactive and then active again is the next
frame synchronization recognized.
In Figure 16, there is a 1-bit data delay. Regardless of the data delay,
transmission can occur without gaps. The last bit of the previous (last) element
in phase 2 is immediately followed by the first data bit of the first element in
phase 1 of the next data frame.
1-bit data delay
P2E12B0 P1E1B15 P1E1B14 P1E1B13
Multichannel Buffered Serial Port (McBSP)
Clocks, Frames, and Data
P1E1B12
39