Connector Pinout And Fpga Connections - Xilinx Spartan-3A User Manual

R
A separate supply provides the same voltage as that applied to the FPGA's I/O Banks 0, 1,
and 2 called VCCO_012. This supply is 3.3V by default. All FPGA I/Os that interface to the
Hirose connector are in Bank 0 or Bank 1.
For improved signal integrity, a majority of pins on the B side of the FX2 connector are tied
to GND.

Connector Pinout and FPGA Connections

Table 15-1
pin connections. The FX2 connect has two rows of connectors, both with 50 connections
each, shown in the table using light yellow shading.
The pin assignment for the connector is identical to that used on the Spartan-3E Starter Kit
board, although the Spartan-3E board pinout includes a few input-only pins. The Spartan-
3A/3AN Starter Kit board pin assignment uses only full I/O pins and are backwards
compatible with the Spartan-3E Starter Kit board.
a
Table 15-1: Hirose 100-Pin FX2 Connector Pinout and FPGA Connections (J17)
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA
Signal Name FPGA Pin
Supply to FPGA VCCO_012
I/O Banks 0, 1, 2
VCCO_012
TMS_B
JTSEL
TDO_FX2
FX2_IO1 A13
FX2_IO2 B13
FX2_IO3 A14
FX2_IO4 B15
FX2_IO5 A15
FX2_IO6 A16
FX2_IO7 A17
FX2_IO8 B17
FX2_IO9 A18
FX2_IO10 C18
FX2_IO11 A19
FX2_IO12 B19
FX2_IO13 A20
FX2_IO14 B20
FX2_IO15 C19
FX2_IO16 D19
FX2_IO17 D18
FX2_IO18 E17
FX2_IO19 D20
FX2_IO20 D21
FX2_IO21 D22
FX2_IO22 E22
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Hirose 100-Pin FX2 Edge Connector (J17)
FX2 Connector
Shared
B
J34 A (top) (bottom)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
FPGA
Pin Signal Name
SHIELD
GND GND
TDO_XC2C
TCK_B
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
123