Power Supply Jacks; Fpga Configuration - Xilinx Virtex-II Pro ML324 User Manual

Detailed Description

2. Power Supply Jacks

One method of delivering power to the FPGA is by way of the power supply jacks. These
jacks are:
•
•
•
•
The following two jacks supply termination voltages to the RocketIO transceivers on the
top and bottom edges of the FPGA:
•
•
Note:
the 3.3V regulator for the System ACE chip.

3. FPGA Configuration

The FPGA can only be configured in JTAG mode using one of the following options:
•
•
•
Using the configuration address DIP switches, one of eight bitstreams stored in the
CompactFlash memory can be accessed through the on-board System ACE controller.
Note:
be bypassed, thus causing no disruption in the JTAG chain.
1. For further information, consult the System ACE CompactFlash Solution (DS080)
12
AVCCAUX
♦
Supplies power to the RocketIO transceivers on the FPGA
VCCAUX
♦
Supplies voltage to the V
VCCO
♦
Supplies I/O voltages to the FPGA
VCORE
♦
Supplies voltage to the core of the FPGA
(Consult the Virtex-II Pro Platform FPGAs: Complete Data Sheet (DS083) at
http://direct.xilinx.com/bvdocs/publications/ds083.pdf
VCORE voltage for the device you are using)
VT_TX (top set and bottom set)
VT_RX (top set and bottom set)
5V must always be applied to the 5V jack or to the external power brick connector to power
Parallel Cable III cable
Parallel Cable IV cable
System ACE configuration controller
When using the flying wire leads or the Parallel Cable IV cable, the System ACE controller will
http://www.xilinx.com/bvdocs/publications/ds080.pdf.).
www.xilinx.com
header and the V
AUX AUX
(1)
Virtex-II Pro ML324 and ML325 Platform
FPGA pins
for the maximum
UG063 (v1.2) May 30, 2006
R