Vck190 Gty Connections; Gty103/104: Pci Express Card Edge Connectivity - Xilinx VCK190 Series User Manual

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GTY103/104: PCI Express Card Edge Connectivity

[Figure 3, callout 15]
The 8-lane PCI Express card edge connector P3 supports operation up to Gen4 x8. P3 supports
data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, 8.0
GT/s for Gen3 applications, and 16.0 GT/s for Gen4 applications. The PCIe transmit and receive
signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe_EP_REFCLK_P/N PCIe
reference clock (routed as a 100Ω differential pair) received from J18 is routed to IDT
85411AMLF U39 1:2 buffer, which retransmits the clock as PCIe_CLK0 and PCIe_CLK1. U39
output Q0 PCIe_CLK0_P/N is routed to GTY103 (PCIe_EP_TX/RX[3:0]_P/N) and output Q1
PCIe_CLK1_P/N is routed to GTY104 (PCIe_TX/RX[7:4]_P/N).
For additional information about the Versal ACAP PCIe functionality, see the Versal ACAP
Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). Additional information about
the PCI Express standard is available at the
The detailed ACAP connections for the feature described in this section are documented in the
VCK190 board XDC file, referenced in
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Figure 19: VCK190 GTY Connections
GTY0
GTY
GTY1
GTY2
GTY3
Bank 106
HSDP
GTY0
GTY
GTY1
GTY2
GTY3
Bank 105
Lane 4
GTY0
GTY
Lane 5
GTY1
Lane 6
GTY2
PCIe
Lane 7
GTY3
Bank 104
GEN4
x8
Lane 0
GTY0
GTY
Lane 1
GTY1
Lane 2
GTY2
Lane 3
GTY3
Bank 103
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
GTY0
GTY
GTY1
GTY2
GTY3
Bank 206
GTY0
GTY
GTY1
GTY2
GTY3
Bank 205
GTY0
GTY
GTY1
MRMAC
GTY2
GTY3
Bank 204
GTY0
GTY
GTY1
MRMAC
GTY2
GTY3
Bank 203
GTY0
GTY
GTY1
GTY2
GTY3
Bank 202
GTY0
GTY
GTY1
MRMAC
GTY2
GTY3
Bank 201
GTY0
GTY
MRMAC GTY1
GTY2
GTY3
Bank 200
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PCI-SIG website.
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