Serial Eprom Booting; No-Booting - Analog Devices VisualDSP++ 3.5 Manual

ADSP-219x DSP Booting

Serial EPROM Booting

The SPI0 port is used when booting from an SPI-compatible EPROM.
The SPI port selects a single serial EPROM device using the
chip select, submits a read command and address
clock consecutive data into memory (internal memory or external mem-
ory) at a clock frequency of HCLK/60. The DSP streams the
SCK
complete boot image in and processes it without further handshake with
the SPI EPROM.
Two types of SPI EEPROM devices are supported: devices of 4K bytes
and smaller (12-bit address range), and those larger than 4K bytes (16-bit
address range). The SPI boot stream may not exceed 64 kilobytes.
This boot operation is controlled by an SPI boot routine in internal ROM
space. While booting via serial EPROM, the highest 16 locations in
page 0 program memory block (
tions of page 0 data memory block (
by the ROM boot routine. Refer to the Application Note EE-145 for SPI
booting examples.

No-booting

When
BMODE2-0
out of hardware reset and begins to execute code from page 1 memory
space (
0x01 0000
the pin (
BMODE0
default, the External Port Interface (EPI) is configured to operate with the
divide-by-128 clock and a read wait-state count of 7.
!
No-boot mode does not use boot-stream format.
After reset, the DSP starts program execution from external address
. When the no-boot option is selected, the DSP typically expects
0x010000
an 8- or 16-bit EPROM or Flash device connected to the memory strobe
3-12
0x7FF0
is strapped to a
000
). The specified packing mode depends on the state of
= 8-bit /24-bit
0 ext
0x00
to ) and the top 272 loca-
0x7FFF
to ) are reserved for use
0xFEF0 0xFFFF
or , the ADSP-219x DSP comes
001
, = 16-bit
int 1 ext
VisualDSP++ Loader Manual
for 16-Bit Processors
pin as a
PF0
, and begins to
/24-bit ). By
int