Blackfin Processor Booting - Analog Devices VisualDSP++ 3.5 Manual

Blackfin Processor Booting

Blackfin Processor Booting
Figure 2-1 is a simplified view of the Blackfin processor's booting
sequence.
.ASM, .C, .CPP
Source Files
Figure 2-1. Blackfin Processors: Booting Sequence
A Blackfin processor can be booted from an 8- or 16-bit Flash/PROM
memory or an 8-,16-, or 24-bit addressable SPI memory. (24-bit address-
able SPI memory booting supported only on ADSP-BF531/BF532/BF533
processors.) There is also a no-boot option (bypass mode), in which execu-
tion occurs from a 16-bit external memory.
At powerup, after the reset, the processor transitions into a boot mode
sequence configured by the
bits in the System Reset Configuration Register (
are dedicated mode-control pins; that is, no other functions are shared
with these pins.
2-2
.DOJ
Assembler
and/or
Compiler
Target System
Booting
upon
RESET
ADSP-BF53x
Processor
pins. These pins can be read through
BMODE
.DXE
Linker
.LDR
External
Memory
). The
SYSCR BMODE
VisualDSP++ Loader Manual
for 16-Bit Processors
Loader
pins