Adsp-Bf531/Bf532/Bf533 Processor Spl Memory Boot Sequence - Analog Devices VisualDSP++ 3.5 Manual

Blackfin Processor Booting
ADSP-BF531/BF532/BF533 Processor SPl Memory Boot Se-
quence
The ADSP-BF531/BF532/BF533 processors support booting from 8-,
16-, or 24-bit addressable SPI memories (
To determine the memory type connected to the processor (8-, 16-, or
24-bit), the processor sends signals to the SPI memory until it responds
back. The SPI memory does not respond back until it is properly
addressed.
The on-chip boot ROM does the following.
1. Sends a
2. Sends an address byte,
3. Sends another byte,
zero. If the byte is a zero, an 8-bit addressable SPI memory device
is connected.
4. If the incoming byte is not a zero, the on-chip boot ROM sends
another byte,
byte is a zero, a 16-bit addressable SPI memory device is
connected.
5. If the incoming byte is not a zero, the on-chip boot ROM sends
another byte,
last byte is a zero when a 24-bit addressable SPI memory device is
connected.
2-26
command,
READ 0x03
0x00
, and verifies if the incoming byte is a
0x00
, and verifies if the incoming byte is a zero. If the
0x00
, and verifies if the incoming byte is a zero. The
0x00
BMODE = 11
, then does a dummy
, then does a dummy
VisualDSP++ Loader Manual
).
.
READ
.
READ
for 16-Bit Processors