Second-Stage Loader Restrictions - Analog Devices VisualDSP++ 3.5 Manual

Blackfin Processor Booting
Bank 2 (
"
Bank 3 (
"
!
SDRAM must be initialized by user code before any instructions or
data are loaded into it.
For more information see

Second-Stage Loader Restrictions

When using the second-stage loader:
• The bottom of L2 memory must be reserved during booting. These
locations can be reallocated during runtime. The following loca-
tions pertain to the current second-stage loaders.
For 8- and 16-bit PROM/Flash booting, reserve
"
0xF003 FE00–0xF003 FFFF
For 8- and 16-bit addressable SPI booting, reserve
"
0xF003 FD00–0xF003 FFFF
• If segments reside in SDRAM memory, configure the SDRAM reg-
isters accordingly in the second-stage loader kernels before booting.
Modify section of code called "
"
second-stage loader and rebuild the second-stage loader.
• Any segments residing in L1 instruction memory
(
0xFFA0 0000–0xFFA0 3FFF
Declare segments, within the .
"
instruction memory at starting locations that are 8-byte
aligned (for example,
0xFFA0 0010
Or use the
"
2-14
)
0x1000 0000
)
0x1800 0000
"Using Second-Stage Loader" on page
) must be 8-byte aligned.
0xFFA0 0000
, and so on).
directives in the application code.
.ALIGN 8;
(last 512 bytes).
(last 768 bytes).
" in the
SDRAM setup
file, that reside in L1
LDF
,
0xFFA0 0008
VisualDSP++ Loader Manual
for 16-Bit Processors
2-49.
,