Analog Devices VisualDSP++ 3.5 Manual page 48

Blackfin Processor Booting
ADSP-BF531/BF532/BF533 Processor
L1 Memory
0xEF00 0000
On-Chip
Boot ROM
Figure 2-9. ADSP-BF531/BF532/BF533 Processors: Booting Sequence
The booting sequence for ADSP-BF531, ADSP-BF532, and
ADSP-BF533 processors is quite different from that of ADSP-BF535 pro-
cessors. The on-chip boot ROM for the former processors behaves similar
to the second-stage loader of ADSP-BF535 processors. The boot ROM
has the capability to parse address and count information for each boota-
ble block. This alleviates the need for a second-stage loader for
ADSP-BF531/BF532/BF533 processors because a full application can be
booted to the various memories with just the on-chip boot ROM.
The loader converts the application code (.
parsing the code and creating a file that consists of different blocks. Each
block is encapsulated within a 10-byte header which is illustrated in
Figure 2-9 and detailed in the following section. These headers, in turn,
are read and parsed by the on-chip boot ROM during booting. The
10-byte header provides all the information the on-chip boot ROM
requires: where to boot the block to, how many bytes to boot in, and what
to do with the block.
2-18
PROM/Flash or SPI Device
Block 1
A
Block 3
........
10-Byte Header for Block 1
Block 1
10-Byte Header for Block 2
Block 2
App.
Code/
10-Byte Header for Block 3
Data
Block 3
........
10-Byte Header for Block n
Block n
SDRAM
Block 2
) into the loadable file by
DXE
VisualDSP++ Loader Manual
for 16-Bit Processors