Analog Devices VisualDSP++ 3.5 Manual page 54

Blackfin Processor Booting
P0.H = (EBIU_SDRRC >> 16) & 0xFFFF;
R0 = 0x074A(Z);
W[P0] = R0;
SSYNC;
P0.L = EBIU_SDBCTL & 0xFFFF;
/* SDRAM Memory Bank Control Register */
P0.H = (EBIU_SDBCTL >> 16) & 0xFFFF;
R0 = 0x0001(Z);
W[P0] = R0;
SSYNC;
P0.L = EBIU_SDGCTL & 0xFFFF;
/* SDRAM Memory Global Control Register */
P0.H = (EBIU_SDGCTL >> 16) & 0xFFFF;//
R0.L = 0x998D;
R0.H = 0x0091;
[P0] = R0;
SSYNC;
/*********************Post-Init Section************************/
L3 = [SP++]; L2 = [SP++]; L1 = [SP++]; L0 = [SP++];
M3 = [SP++]; M2 = [SP++]; M1 = [SP++]; M0 = [SP++];
B3 = [SP++]; B2 = [SP++]; B1 = [SP++]; B0 = [SP++];
I3 = [SP++]; I2 = [SP++]; I1 = [SP++]; I0 = [SP++];
(p5:0) = [SP++];
(r7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
/************************************************************/
RTS;
2-24 VisualDSP++ Loader Manual
for 16-Bit Processors