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System Memory Design Guidelines
6.3.2
System Memory 3-DIMM Layout Guidelines
Figure 39. System Memory 3-DIMM Routing Topologies
In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace
edges must be at least 30 mils from any other non-system memory signal trace edge.
Table 19. System Memory 3-DIMM Solution Space
Signal
Top.
Width
SCS[5:4]#
4
SCS[3:2]#
3
SCS[1:0]#
2
SMAA[7:4]
6
SMAB[7:4]#
7
SMAC[7:4}
8
SCKE[5:4]
4
SCKE[3:2]
3
SCKE[1:0]
2
SMD[63:0]
1
SDQM[7:0]
1
SCAS#,
5
SRAS#, SWE#
SBS[1:0],
5
SMAA[12:8,3:0]
74
82815
Topology 1
Topology 2
Topology 3
Topology 4
Topology 5
10
Topology 6
G
10
Topology 7
G
10
Topology 8
G
Trace (mils)
A
Spacing
Min.
Max.
5
10
5
10
5
10
10
10
10
10
10
10
10
10
10
10
10
10
5
10
1.75
4
10
10
1.5
3.5
5
10
5
10
A
C
D
E
F
C
D
E
Trace Lengths (inches)
B
C
Min.
Max.
Min.
Max.
Min.
1
1
4.5
2
4
2
3
3
4
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
®
Intel
815 Chipset Platform Design Guide
DIMM 0
DIMM 1
DIMM 2
B
B
B
B
sys_mem_3DIMM_routing_topo
D
E
F
Max.
Min.
Max.
Min.
Max.
1
4.5
4.5
4
2
4
3
4
4
1
4
1
4
R
G
Min.
Max.
0.4
0.5
0.4
0.5
0.4
0.5
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