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10.2.4
Secondary IDE Connector Requirements
Figure 61. Resistor Schematic for Secondary IDE Connectors
Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1
of the IDE connectors as the IDE reset signal. Because of high loading, the PCI_RST# signal
should be buffered.
22
determined for each unique motherboard design, based on signal quality.
IRQ14 and IRQ15 each require an 8.2 k pull-up resistor to VCC.
A 1 k pull-up to 5V is required on PIORDY and SIORDY.
A 470
A 5.6 k pull-down is required on PDREQ and SDREQ.
The primary IDE connector uses IRQ14, and the secondary IDE connector uses IRQ15.
There is no internal pull-up or pull-down on PDD7 or SDD7 of the ICH. Devices must not
have a pull-up resistor on DD7. It is recommended that a host have a 10 k pull-down resistor
on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as
required by the ATA-4 specification).
®
Intel
815 Chipset Platform Design Guide
PCIRST_BUF#*
SDD[15:8]
SDD[7]
SDD[6:0]
SDA[2:0]
SDCS1#
SDCS3#
SDIOR#
SDIOW#
SDDREQ
5V
1 k
SIORDY
IRQ15
SDDACK#
ICH
* Due to high loading, PCIRST# must be buffered.
to 47
series resistors are required on RESET#. The correct value should be
pull-down is required on pin 28 of each connector.
5V
5.6
10 k
k
8.2 k
I/O Subsystem
22 - 47
Reset#
470
CSEL
Pin 32
N.C.
IDE_resistor_schem_secondary
117
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