Host Side Cable Detection; Figure 58. Host-Side Ide Cable Detection - Intel 815 Design Manual

I/O Subsystem
10.2.1

Host Side Cable Detection

BIOS Detects Cable Type Using GPIOs
Host-side detection requires the use of two GPI pins (one per IDE controller). The proper way to
connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 58. All
Ultra ATA/66 devices have a 10 k pull-up resistor to 5V. Most GPIO pins on the ICH and all
GPIs on the FWH are not 5V tolerant. This requires a resistor divider so that 5V will not be driven
to the ICH or FWH pins. The proper value of the series resistor is 15 k (as shown in the
following figure). This creates a 10 k /15 k resistor divider and will produce approximately 3V
for a logic high. This mechanism allows the host to sample PDIAG#/CBLID#, after diagnostics. If
PDIAG#/CBLIB# is high, then there is 40-conductor cable in the system and ATA modes 3 and 4
should not be enabled. If PDIAG#/CBLID# is low, then there is an 80-conductor cable in the
system.

Figure 58. Host-Side IDE Cable Detection

ICH
ICH
114
To secondary
IDE connector
GPIO
GPIO
15 k
To secondary
IDE connector
GPIO
GPIO
15 k
40-conductor
cable
80-conductor
IDE cable
Open
®
Intel 815 Chipset Platform Design Guide
R
IDE Drive
5 V
10 k
PDIAG
IDE Drive
5 V
10 k
PDIAG
IDE_cable_det_host