Intel 815 Design Manual page 48

System Bus Design Guidelines
Minimizing Cross-Talk
The following general rules minimize the impact of cross-talk in a high-speed AGTL/AGTL+ bus
design:
Maximize the space between traces. Where possible, maintain a minimum of 10 mils
(assuming a 5-mil trace) between trace edges. It may be necessary to use tighter spacing when
routing between component pins. When traces must be close and parallel to each other,
minimize the distance that they are close together and maximize the distance between the
sections when the spacing restrictions are relaxed.
Avoid parallelism between signals on adjacent layers, if there is no AC reference plane
between them. As a rule of thumb, route adjacent layers orthogonally.
Since AGTL/AGTL+ is a low-signal-swing technology, it is important to isolate
AGTL/AGTL+ signals from other signals by at least 25 mils. This will avoid coupling from
signals that have larger voltage swings (e.g., 5V PCI).
AGTL/AGTL+ signals must be well isolated from system memory signals. AGTL/AGTL+
signal trace edges must be at least 30 mils from system memory trace edges within 100 mils of
the ball of the GMCH.
Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the
nominal characteristic impedance within the AGTL/AGTL+ specification. This can be done
by minimizing the height of the trace from its reference plane, which minimizes cross-talk.
Route AGTL/AGTL+ address, data, and control signals in separate groups to minimize cross-
talk between groups. Keep at least 15 mils between each group of signals.
Minimize the dielectric used in the system. This makes the traces closer to their reference
plane and thus reduces the cross-talk magnitude.
Minimize the dielectric process variation used in the PCB fabrication.
Minimize the cross-sectional area of the traces. This can be done by means of narrower traces
and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher
trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along
the trace.
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Intel 815 Chipset Platform Design Guide
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