Table 6. Intel Pentium; Calculations - Intel 815 Design Manual

System Bus Design Guidelines
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Table 6. Intel Pentium
IC Parameters
Clock to Output maximum
(T
CO _ MAX
Clock to Output minimum
(T )
CO _ MIN
Setup time (T
Hold time (T
NOTES:
1. All times in nanoseconds.
2. Numbers in table are for reference only. These timing parameters are subject to change. Check the
appropriate component datasheet for the valid timing parameter values.
3. T
SU _ MIN
Table 7 contains an example AGTL+ initial maximum flight time, and Table 8 contains an
example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium
III processor and the Intel 815 chipset platform's system bus. Note that assumed values were used
for the clock skew and clock jitter.
Note: The clock skew and clock jitter values depend on the clock components and the distribution
method chosen for a particular design and must be budgeted into the initial timing equations, as
appropriate for each design.
Table 7and Table 8 were derived assuming the following:
CLK
SKEW
50 ps by tying the two host clock outputs together (i.e., "ganging") at the clock driver output
pins, and that the PCB clock routing skew is 150 ps. The system timing budget must assume
0.175 ns of clock driver skew if outputs are not tied together as well as the use of a clock
driver that meets the Intel CK-815 Clock Synthesizer/Driver Specification.)
CLK
JITTER
See the respective processor's datasheet, the appropriate Intel 815 chipset platform documentation,
and the Intel
specifications. Exact details regarding the host clock routing topology are provided with the
platform design guideline.
44
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III Processor AGTL/AGTL+ Parameters for Example Calculations
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Intel Pentium
3.25 ns (for 66/100/133 MHz system bus speeds)
)
0.40 ns (for 66/100/133 MHz system bus)
) 1.20 ns (for BREQ Lines)
SU _ MIN
0.95 ns (for all other AGTL/AGTL+ Lines @
133 MHz)
1.20 ns (for all other AGTL/AGTL+ Lines @
66/100 MHz)
) 1.0 ns (for 66/100/133 MHz system bus speeds)
HOLD
= 2.65 ns assumes that the GMCH sees a minimum edge rate equal to 0.3 V/ns.
= 0.20 ns (Note: This assumes that the clock driver pin-to-pin skew is reduced to
= 0.250 ns
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CK-815 Clock Synthesizer/Driver Specification for details on clock skew and jitter
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III Processor at 133 MHz System
Bus
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Intel 815 Chipset Platform Design Guide
R
GMCH Notes
4.1 ns 1, 2
1.05 ns 1, 2
2.65 ns 1, 2,3
0.10 ns 1