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5
ICH, PART 1
D
16,17,29
AD[31:0]
VCC3_3
C
ADM1023
U1
16,17,29
C_BE#[3:0]
5
PCLK_0/ICH
16,17,29,36
FRAME#
B
16,17,29,36
DEVSEL#
16,17,29,36
IRDY#
16,17,29,36
TRDY#
16,17,29,36
STOP#
6,9,14,15,16,17,18,19,24,29
PCIRST#
16,17,36
PLOCK#
16,17,29
PAR
16,17,29,36
SERR#
9,16,17,29
PCI_PME#
17,36
PCPCI_REQ#A
17
PCPCI_GNT#A
36
REQ#B/GPIO1
36
GNT#B/GPIO17
A
5
4
VCC3_3
U21-1
AD[31:0]
AD0
G2
AD0
AD1
G4
AD1
AD2
F2
AD2
AD3
F3
AD3
AD4
F4
AD4
AD5
F5
AD5
AD6
E1
AD6
AD7
E2
AD7
AD8
D1
AD8
AD9
D3
AD9
AD10
E4
AD10
AD11
C2
INTEL 82801AA
AD11
AD12
C1
AD12
AD13
B1
AD13
AD14
D4
AD14
AD15
C3
AD15
AD16
A4
AD16
AD17
B4
AD17
AD18
C5
AD18
AD19
C6
AD19
AD20
B5
AD20
AD21
E7
AD21
AD22
A6
AD22
AD23
B6
PCI
AD23
AD24
D7
AD24
AD25
B8
AD25
AD26
A7
AD26
AD27
A8
AD27
AD28
B7
AD28
AD29
C9
AD29
AD30
D8
AD30
AD31
C7
AD31
C_BE#[3:0]
C_BE#0
D2
C_BE#0
C_BE#1
B2
C_BE#1
C_BE#2
A3
C_BE#2
C_BE#3
D6
C_BE#3
PCLK_0/ICH
C14
PCICLK
FRAME#
B3
FRAME#
DEVSEL#
D9
DEVSEL#
IRDY#
A2
IRDY#
TRDY#
C4
TRDY#
STOP#
D5
STOP#
PCIRST#
J5
PCIRST#
PLOCK#
B9
PLOCK#
PAR
A9
PAR
SERR#
A1
SERR#
PCI_PME#
K1
PME#
PCPCI_REQ#A
N6
REQ#A/GPIO0
PCPCI_GNT#A
P5
GNT#A/GPIO16
REQ#B/GPIO1
P4
PC/PCI
REQ#B/GPIO1/REQ5#
GNT#B/GPIO17
R5
GNT#B/GPIO17/GNT5#
C312
10PF
82815 ICH
No Pop
4
3
VCC1_8
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
CPU
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
HL0
HL1
PART 1
HL2
HL3
HL4
HL5
HL6
HUB I/F
HL7
HL8
HL9
HL10
HLSTB
HLSTB#
HCOMP
HUBREF
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
IRQ14
IRQ
IRQ15
APICCLK
APICD1
APICD0
SERIRQ
REQ#0
REQ#1
REQ#2
REQ#3
GNT#0
PCI
GNT#1
GNT#2
GNT#3
GNT4#
REQ4#
HL11
3
2
A20M#
A20M# 4,36
F13
E12
CPUSLP#
CPUSLP#
4,36
F15
FERR#
FERR#
4,36
IGNNE#
IGNNE#
4,36
B17
INIT#
INIT#
4,14,36
E15
INTR
INTR
4,36
E14
NMI
NMI
4,36
B16
F14
SMI#
SMI#
4,36
STPCLK#
STPCLK# 4,36
A17
RCIN#
RCIN#
15,36
A15
A20GATE
A20GATE 15,36
B15
HL[10:0]
HL[10:0]
8,39
HL0
D17
HL1
E17
HL2
VCC1_8
F17
HL3
G16
HL4
J15
HL5
K16
HL6
K17
HL7
R178
L17
HL8
40 1%
H15
HL9
J17
HL10
Place R178
J14
as close as
HLSTB
HLSTB
8,39
G17
possible to
HLSTB#
HLSTB#
8,39
ICH
H17
IHCOMP_PU
M17
HUBREF
HUBREF
7,8,39
J13
PIRQ#A
PIRQ#A
9,16,17,29,36
C291
D10
PIRQ#B
PIRQ#B
9,16,17,36
0.1UF
A10
PIRQ#C
PIRQ#C
16,17,36
B10
PIRQ#D
PIRQ#D
16,17,36
Place C291
C10
as close as
possible to
IRQ14
IRQ14
18,36
ICH
P11
IRQ15
IRQ15
18,36
N14
APICCLK_ICH
APICCLK_ICH
5
C16
APICD1
APICD1
4,36
C17
APICD0
APICD0
4,36
E16
SERIRQ
SERIRQ
15,17,36
R4
PREQ#0
PREQ#0
36
A14
PREQ#1
PREQ#1
16,36
B13
PREQ#2
PREQ#2
17,36
B12
PREQ#3
PREQ#3
29,36
D12
PGNT#0
PGNT#0
36
A13
PGNT#1
PGNT#1
16,36
VCC3_3
C13
PGNT#2
PGNT#2
17,36
A12
PGNT#3
PGNT#3
29,36
C12
RESV0PU
R213
8.2K
A11
1
2
RESV1PU
B11
1
2
RESV2RD
R212
F16
1
2
R173
0K
8.2K
Don't Stuff R173
For Test/Debug
Title:
INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD
ICH, PART 1
Platform Apps Engineering
int e l
1900 Prairie City Road
R
Folsom, CA 95630
2
1
D
C
B
A
REV.
1.0
Last Revision Date:
3-26-01
Sheet:
12
40
of
1
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