Timing Specifications; General Ac Timing - Analog Devices TigerSHARC ADSP-TS201S Specifications

ADSP-TS201S

TIMING SPECIFICATIONS

With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
TS201S processor has few calculated (formula-based) values.
For information on ac timing, see
information on link port transfer timing, see
Voltage, Differential-Signal (LVDS) Electrical Characteristics,
and Timing on Page 30.

General AC Timing

Timing is measured on signals when they cross the 1.25 V level
as described in Figure 15 on Page
onds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
Table 21. AC Asynchronous Signal Specifications
Name
1
IRQ3–0
1
DMAR3–0
2
FLAG3–0
3
TMR0E
1
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
2
For output specifications on FLAG3–0 pins, see
3
This pin is a strap option. During reset, an internal resistor pulls the pin low.
Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time
Parameter Description
1
t Core Clock Cycle Time
CCLK
1
CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the
CCLK
General AC Timing. For
Link Port Low
29. All delays (in nanosec-
Description
Interrupt Request
DMA Request
FLAG3–0 Input
Timer 0 Expired
Table 29.
t
CCLK
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
Rev. C | Page 24 of 48 | December 2006
The general ac timing data appears in
ac specifications are measured with the load specified in
Figure 36 on Page 38, and with the output drive strength set to
strength 4. In order to calculate the output valid and hold times
for different load conditions and/or output drive strengths, refer
to Figure 37 on Page 38 through
Fall Time vs. Load Capacitance) and
put Valid vs. Load Capacitance and Drive Strength).
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
FLAG3–0, and TMR0E pins appears in
Pulse Width Low (Min)
2 × t ns
SCLK
2 × t ns
SCLK
2×t ns
SCLK
4×t ns
SCLK
Grade = 060 (600 MHz)
Min Max
1.67 12.5
Ordering Guide on Page
Table 22 and Table
Figure 44 on Page 39
Figure 45 on Page 39
Table 21.
Pulse Width High (Min)
2 × t ns
SCLK
2 × t ns
SCLK
2×t ns
SCLK
—
Grade = 050 (500 MHz)
Min Max
2.0 12.5
) divided by the system clock ratio
SCLK
46.
29. All
(Rise and
(Out-
Unit
ns