Link Port-Data Out Timing - Analog Devices TigerSHARC ADSP-TS201S Specifications

Link Port—Data Out Timing
Table 32 with Figure 18, Figure
Figure 22, and Figure 23 provide the data out timing for the
LVDS link ports.
Table 32. Link Port—Data Out Timing
Parameter Description
Outputs
t Rising Edge (Figure
REO
t Falling Edge (Figure
FEO
t LxCLKOUT Period
LCLKOP
t LxCLKOUT High
LCLKOH
t LxCLKOUT Low
LCLKOL
t LxCLKOUT Jitter
COJT
t LxDATO Output Setup
LDOS
t LxDATO Output Hold
LDOH
t Delay from LxACKI rising edge to first transmission
LACKID
clock edge (Figure
t LxBCMPO Valid
BCMPOV
t LxBCMPO Hold
BCMPOH
Inputs
t LxACKI low setup to guarantee that the transmitter
LACKIS
stops transmitting
LxACKI high setup to guarantee that the transmitter
continues its transmission without any interruption
(Figure 23)
t LxACKI High Hold Time
LACKIH
1
Timing is relative to the 0 differential voltage (V
2
LCR (link port clock ratio) = 1, 1.5, 2, or 4. t
3
For the cases of t = 2.0 ns and t
LCLKOP
4
LCR= 1.
5
LCR= 1.5.
6
LCR= 2.
7
LCR= 4.
8
The t and t values include LCLKOUT jitter.
LDOS LDOH
TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × t
9
19, Figure 20, Figure 21,
19)
19)
(Figure 18)
(Figure 18)
(Figure 18)
(Figure 18)
(Figure 20)
(Figure 20)
21)
(Figure 21)
(Figure 22)
(Figure 22)
(Figure 23)
= 0).
OD
is the core period.
CCLK
= 12.5 ns, the effect of t specification on output period must be considered.
LCLKOP COJT
Rev. C | Page 31 of 48 | December 2006
Min
Greater of 2.0 or
0.9 × LCR × t
1, 2, 3
CCLK
0.4 × t
1
LCLKOP
0.4 × t
1
LCLKOP
0.25 × LCR × t – 0.10 × t
CCLK
0.25 × LCR × t – 0.15 × t
CCLK
0.25 × LCR × t – 0.30 × t
CCLK
0.25 × LCR × t – 0.10 × t
CCLK
0.25 × LCR × t – 0.15 × t
CCLK
0.25 × LCR × t – 0.30 × t
CCLK
3 × TSW – 0.5
1, 9
16 × LCR × t
1, 2
CCLK
0.51
. For a 1-bit link, it is 8 × LCR × t
CCLK
ADSP-TS201S
Max
350
350
Smaller of 12.5 or
1.1 × LCR × t
0.6 × t
LCLKOP
0.6 × t
LCLKOP
±150
4, 5, 6
±250
7
1, 4, 8
CCLK
1, 5, 6, 8
CCLK
1, 7, 8
CCLK
1, 4, 8
CCLK
1, 5, 6, 8
CCLK
1, 7, 8
CCLK
16 × LCR × t
2 × LCR × t
ns.
CCLK
Unit
ps
ps
1, 2, 3
ns
CCLK
1
ns
1
ns
ps
ps
ns
ns
ns
ns
ns
ns
1, 2
ns
CCLK
1, 2
ns
CCLK
ns
ns
ns