Analog Devices TigerSHARC ADSP-TS201S Specifications page 18

ADSP-TS201S
Table 11. Pin Definitions—Link Ports
Signal Type
LxDATO3–0P O
LxDATO3–0N O
LxCLKOUTP O
LxCLKOUTN O
LxACKI I (pd)
LxBCMPO O (pu)
LxDATI3–0P I
LxDATI3–0N I
LxCLKINP I/A
LxCLKINN I/A
LxACKO O
LxBCMPI I (pd_l)
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
Ω
5 k ; pu = internal pull-up 5 k
Ω
pull-up 500 on DSP ID = 0; pd_m = internal pull-down 5 k
Ω
= internal pull-up 40 k ; pd_l = internal pull-down 50 k
Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω
imately 5 k to V , nc = not connected; na = not applicable (always used); V
DD_IO
Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable
Signal Type
CONTROLIMP0 I (pd)
CONTROLIMP1 I (pu)
DS2, 0 I (pu)
DS1 I (pd)
ENEDREG I (pu)
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
Ω
5 k ; pu = internal pull-up 5 k
Ω
pull-up 500 on DSP ID = 0; pd_m = internal pull-down 5 k
Ω
= internal pull-up 40 k . For more pull-down and pull-up information, see
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω
imately 5 k to V , nc = not connected; na = not applicable (always used); V
DD_IO
Term Description
nc Link Ports 3–0 Data 3–0 Transmit LVDS P
nc Link Ports 3–0 Data 3–0 Transmit LVDS N
nc Link Ports 3–0 Transmit Clock LVDS P
nc Link Ports 3–0 Transmit Clock LVDS N
nc Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
nc Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed. The pull-up
resistor is present on L0BCMPO only. At reset, the L1BCMPO, L2BCMPO, and L3BCMPO
pins are strap pins. For more information, see
V Link Ports 3–0 Data 3–0 Receive LVDS P
DD_IO
V Link Ports 3–0 Data 3–0 Receive LVDS N
DD_IO
V Link Ports 3–0 Receive Clock LVDS P
DD_IO
V Link Ports 3–0 Receive Clock LVDS N
DD_IO
nc Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
V Link Ports 3–0 Block Completion. When the reception is executed using DMA, this
SS
signal indicates to the receiver that the transmitted block is completed.
Ω
; pd_0 = internal pull-down 5 k
Ω
. For more pull-down and pull-up information, see
Term Description
na Impedance Control. As shown in
na normal driver mode and A/D driver mode. When using normal mode (recommended),
the output drive strength is set relative to maximum drive strength according to
Table
where drive strength is continuously controlled to match a specific line impedance as
shown in
na Digital Drive Strength Selection. Selected as shown in
lation, see
not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)
include: CPA, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always
x2 drive strength 7 (100%).
V Connect the ENEDREG pin to V
SS
DRAM power supply.
Ω
; pd_0 = internal pull-down 5 k
Rev. C | Page 18 of 48 | December 2006
Ω
on DSP ID = 0; pu_0 = internal pull-up 5 k
Ω
on DSP bus master; pu_m = internal pull-up 5 k
= connect directly to V
DD_IO
Table
14. When using A/D mode, the resistance control operates in the analog mode,
Table 14.
Output Drive Currents on Page
. Connect the V
SS
Ω
on DSP ID = 0; pu_0 = internal pull-up 5 k
Ω
on DSP bus master; pu_m = internal pull-up 5 k
Electrical Characteristics on Page
= connect directly to V
DD_IO
Table 16 on Page 20.
Ω
on DSP ID = 0; pu_od_0 = internal
Ω
on DSP bus master; pu_ad
Electrical Characteristics on
Ω
to V ; epu = external pull-up approx-
SS
; V = connect directly to V
DD_IO SS
13, the CONTROLIMP1–0 pins select between
Table 14. For drive strength calcu-
36. The drive strength for some pins is preset,
pins to a properly decoupled
DD_DRAM
Ω
on DSP ID = 0; pu_od_0 = internal
Ω
on DSP bus master; pu_ad
22.
Ω
to V ; epu = external pull-up approx-
SS
; V = connect directly to V
DD_IO SS
SS
SS