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Table 23. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter
Description
1, 2, 3
t
System Clock Cycle Time
SCLK
t
System Clock Cycle High Time
SCLKH
t
System Clock Cycle Low Time
SCLKL
t
System Clock Transition Time—Falling Edge
SCLKF
t
System Clock Transition Time—Rising Edge
SCLKR
5, 6
t
System Clock Jitter Tolerance
SCLKJ
1
For more information, see
Table 3 on Page
2
For more information, see Clock Domains on Page 9.
3
The value of (t
/ SCLKRAT2-0) must not violate the specification for t
SCLK
4
System clock transition times apply to minimum SCLK cycle time (t
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
SCLK
Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
Parameter
Description
t
Test Clock (JTAG) Cycle Time
TCK
t
Test Clock (JTAG) Cycle High Time
TCKH
t
Test Clock (JTAG) Cycle Low Time
TCKL
TCK
4
12.
.
CCLK
) only.
SCLK
t
SCLK
t
t
SCLKH
SCLKL
Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time
t
TCK
t
t
TCKH
TCKL
Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
Rev. C | Page 25 of 48 | December 2006
SCLKRAT = 4×, 6×, 8×, 10×, 12× SCLKRAT = 5×, 7×
Min
Max
8
50
0.40 × t
0.60 × t
SCLK
SCLK
0.40 × t
0.60 × t
SCLK
SCLK
—
1.5
—
1.5
—
500
t
SCLKJ
Min
Greater of 30 or t
12
12
ADSP-TS201S
Min
Max
8
50
0.45 × t
0.55 × t
SCLK
SCLK
0.45 × t
0.55 × t
SCLK
SCLK
—
1.5
—
1.5
—
500
t
t
SCLKF
SCLKR
Max
Unit
× 4
—
ns
CCLK
—
ns
—
ns
Unit
ns
ns
ns
ns
ns
ps
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