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Table 29. AC Signal Specifications (Continued)
(All values in this table are in nanoseconds.)
Name
8
DS2–0
8
SCLKRAT2–0
ENEDREG
9, 10
STRAP SYS
11, 12
JTAG SYS
1
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2
For input specifications on FLAG3–0 pins, see
3
These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4
For additional requirement details, see
5
RST_IN clock reference is the falling edge of SCLK.
6
TDO output clock reference is the falling edge of TCK.
7
Reference clock depends on function.
8
These pins may change only during reset; recommend connecting it to V
9
STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.
10
Specifications applicable during reset only.
11
JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,
IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0,
L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP,
L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0,
L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO,
L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0,
SCLKRAT2–0, DS2–0, ENEDREG.
12
JTAG system output timing clock reference is the falling edge of TCK.
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
Description
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Connected to V
Strap Pins
JTAG System Pins
Table
21.
Reset and Booting on Page
9.
1.25V
OUTPUT
VALID
OUTPUT
DISABLE
Figure 15. General AC Parameters Timing
Rev. C | Page 29 of 48 | December 2006
—
—
—
—
—
—
SS
1.5
0.5
+2.5
+10.0
/V
.
DD_IO
SS
t
t
OR
SCLK
TCK
INPUT
1.25V
SETUP
1.25V
ADSP-TS201S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+12.0
–1.0
—
—
INPUT
HOLD
OUTPUT
HOLD
OUTPUT
ENABLE
—
—
—
SCLK
TCK
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