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ADSP-TS201S
Table 25. Power-Up Timing
Parameter
Timing Requirement
t
V
Stable After V
VDD_DRAM
DD_DRAM
1
For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.
V
DD
V
DD_A
V
DD_IO
V
DD_DRAM
Table 26. Power-Up Reset Timing
Parameter
Timing Requirements
t
RST_IN Deasserted After V
RST_IN_PWR
Strap Pins Stable
1
t
TRST Asserted During Power-Up Reset
TRST_IN_PWR
Switching Characteristic
t
RST_OUT Deasserted After RST_IN Deasserted
RST_OUT_PWR
1
Applies after V
, V
, V
, V
DD
DD_A
DD_IO
RST_IN
RST_OUT
TRST
SCLK, V
V
DD,
DD_A,
V
V
DD_IO,
DD_DRAM
STATIC/STRAP PINS
1
, V
, V
Stable
DD
DD_A
DD_IO
t
VDD_DRAM
, V
, V
DD
DD_A
DD_IO
, and SCLK are stable and before RST_IN deasserted.
DD_DRAM
Figure 13. Power-Up Reset Timing
Rev. C | Page 26 of 48 | December 2006
Figure 12. Power-Up Timing
, V
, SCLK, and Static/
DD_DRAM
t
t
RST_IN_PWR
RST_OUT_PWR
t
TRST_IN_PWR
Min
Max
>0
Min
Max
2
100 × t
SCLK
1.5
Unit
ms
Unit
ms
ns
ms
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