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ADSP-TS201S
POWER DOMAINS
The ADSP-TS201S processor has separate power supply con-
nections for internal logic (V
buffer (V
), and internal DRAM (V
DD_IO
Note that the analog (V
) supply powers the clock generator
DD_A
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input V
attention to bypassing the V
FILTERING REFERENCE VOLTAGE AND CLOCKS
Figure 6
and
Figure 7
show possible circuits for filtering V
and SCLK_V
. These circuits provide the reference voltages
REF
for the switching voltage reference and system clock reference.
V
DD_IO
R1
R2
C1
V
SS
R1: 2k
SERIES RESISTOR (±1%)
R2: 2.55k
SERIES RESISTOR (±1%)
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP'S PINS
Figure 6. V
CLOCK DRIVER
*
VOLTAGE OR
V
DD_IO
R1
R2
C1
R1: 2k
SERIES RESISTOR (±1%)
R2: 2.55k
SERIES RESISTOR (±1%)
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP'S PINS
* IF CLOCK DRIVER VOLTAGE > V
Figure 7. SCLK_V
DEVELOPMENT TOOLS
The ADSP-TS201S processor is supported with a complete set
®†
of CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS201S processor.
†
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡
VisualDSP++ is a registered trademark of Analog Devices, Inc.
), analog circuits (V
), I/O
DD
DD_A
) power supply.
DD_DRAM
. Designs must pay critical
DD_A
supply.
DD_A
V
REF
C2
Filtering Scheme
REF
SCLK_V
C2
V
SS
DD_IO
Filtering Scheme
REF
®‡
Rev. C | Page 10 of 48 | December 2006
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for theses tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has archi-
tectural features that improve the efficiency of compiled
C/C++ code.
,
The VisualDSP++ debugger has a number of important
REF
features. Data visualization is enhanced by a plotting package
that offers a significant level of flexibility. This graphical
representation of user data enables the programmer to quickly
determine the performance of an algorithm. As algorithms grow
in complexity, this capability can have increasing significance
on the designer's development schedule, increasing
productivity. Statistical profiling enables the programmer to
nonintrusively poll the processor as it is running the program.
This feature, unique to VisualDSP++, enables the software
developer to passively gather important code execution metrics
without interrupting the real-time characteristics of the
program. Essentially, the developer can identify bottlenecks in
software quickly and efficiently. By using the profiler, the
programmer can focus on those areas in the program that
impact performance and take corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
REF
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
processor development tools, including the color syntax high-
lighting in the VisualDSP++ editor. This capability permits
programmers to:
• Control how the development tools process inputs and
devel-
generate outputs
• Maintain a one-to-one correspondence with the tool's
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
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