Adsp-Ts201S-Specifications; Operating Conditions - Analog Devices TigerSHARC ADSP-TS201S Specifications

ADSP-TS201S—SPECIFICATIONS
Note that component specifications are subject to change with-
out notice. For information on link port electrical
characteristics, see Link Port Low Voltage, Differential-Signal
(LVDS) Electrical Characteristics, and Timing on Page

OPERATING CONDITIONS

Parameter Description
V Internal Supply Voltage
DD
V Analog Supply Voltage
DD_A
V I/O Supply Voltage
DD_IO
V Internal DRAM Supply Voltage
DD_DRAM
T Case Operating Temperature
CASE
T Case Operating Temperature
CASE
V High Level Input Voltage
IH1
V High Level Input Voltage
IH2
V Low Level Input Voltage
IL
I V Supply Current, Typical Activity
DD DD
I V Supply Current, Typical Activity
DD_A DD_A
I V Supply Current, Typical Activity
DD_IO DD_IO
I V Supply Current, Typical Activity
DD_DRAM DD_DRAM
V Voltage Reference
REF
SCLK_V Voltage Reference
REF
1
Specifications vary for different grades (for example, SABP-060, SABP-050, SWBP-050). For more information on part grades, see
2
V specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, WRH, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0,
IH1
RAS, CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.
3
Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in
to 100% duty cycle.
4
V specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.
IH2
5
Applies to input and bidirectional pins.
6
For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices
website.
30.
Test Conditions
@ CCLK = 600 MHz
@ CCLK = 500 MHz
@ CCLK = 600 MHz
@ CCLK = 500 MHz
@ CCLK = 600 MHz
@ CCLK = 500 MHz
2, 3
@ V , V
DD DD_IO
3, 4
@ V , V
DD DD_IO
3, 5
@ V , V
DD DD_IO
6
@ CCLK = 600 MHz, V
@ CCLK = 500 MHz, V
@ CCLK = 600 MHz, V
@ CCLK = 500 MHz, V
6
@ SCLK = 62.5 MHz, V
6
@ CCLK = 600 MHz, V
@ CCLK = 500 MHz, V
Rev. C | Page 21 of 48 | December 2006
= Max
= Max
= Min
= 1.20 V, T = 25°C
DD CASE
= 1.05 V, T = 25°C
DD CASE
= 1.20 V, T = 25°C
DD CASE
= 1.05 V, T = 25°C
DD CASE
= 2.5 V, T = 25°C
DD_IO CASE
= 1.6 V, T = 25°C 060
DD_DRAM CASE
= 1.5 V, T = 25°C 050
DD_DRAM CASE
Table 18, based on the transient duty cycle. The dc case is equivalent
ADSP-TS201S
1
Grade Min Typ Max
060 1.14 1.20 1.26
050 1.00 1.05 1.10
060 1.14 1.20 1.26
050 1.00 1.05 1.10
(all) 2.38 2.50 2.63
060 1.52 1.60 1.68
050 1.425 1.500 1.575
A –40 +85
W –40 +105
(all) 1.7 3.63
(all) 1.9 3.63
(all) –0.33 +0.8
060 2.90
050 2.06
060 25 55
050 20 50
(all) 0.15
0.28 0.43
0.25 0.40
(all) (V ×0.56)±5%
DD_IO
(all) (V × 0.56) ±5%
_
CLOCK DRIVE
Ordering Guide on Page 46.
Unit
V
V
V
V
V
V
V
°C
°C
V
V
V
A
A
mA
mA
A
A
A
V
V