Timing Specifications - Analog Devices MicroConverter ADuC812 User Manual

ADuC812

TIMING SPECIFICATIONS

Parameter
CLOCK INPUT (External Clock Driven XTAL1)
t XTAL1 Period
CK
t XTAL1 Width Low
CKL
t XTAL1 Width High
CKH
t XTAL1 Rise Time
CKR
t XTAL1 Fall Time
CKF
4
t ADuC812 Machine Cycle Time
CYC
NOTES
1
AC inputs during testing are driven at DV
a Logic 0.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V /V level occurs.
OH OL
3 for Port0, ALE, PSEN outputs = 100 pF; C
C
LOAD
4
ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.
DV – 0.5V
DD
0.45V
1, 2, 3
(AV = DV = 3.0 V or 5.0 V
DD DD
Min
20
20
– 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V
DD
for all other outputs = 80 pF unless otherwise noted.
LOAD
t
CKH
0.2V + 0.9V
CC
TEST POINTS
0.2V – 0.1V
CC
10%. All specifications T
12 MHz Variable Clock
Typ Max Min
83.33 62.5
20
20
20
20
1
t
CKR
t
CKL
t
CK
V – 0.1V
LOAD
TIMING
V REFERENCE
LOAD
POINTS
V + 0.1V
LOAD
= T to T unless otherwise noted.)
A MIN MAX
Typ Max Unit
1000 ns
ns
ns
20 ns
20 ns
µs
12t
CK
min for a Logic 1 and V
IH
t
CKF
V – 0.1V
LOAD
V
LOAD
V – 0.1V
LOAD
Figure
50
50
50
50
50
max for
IL