Analog Devices TigerSHARC ADSP-TS201S Specifications page 44

Analog devices, inc. embedded processor specification sheet
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ADSP-TS201S
Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)
Ball No. Signal Name
U1
MSSD0
U2
RST_OUT
U3
ID2
U4
DS1
U5
V
DD_IO
U6
V
DD
U7
V
DD
U8
V
SS
U9
V
SS
U10
V
DD
U11
V
DD_DRAM
U12
V
SS
U13
V
SS
U14
V
SS
U15
V
SS
U16
V
SS
U17
V
SS
U18
V
DD
U19
V
DD
U20
V
DD_IO
U21
L1CLKINN
U22
L1CLKINP
U23
L1DATI1_N
U24
L1DATI1_P
AA1
FLAG2
AA2
FLAG1
AA3
IRQ3
AA4
V
SS
AA5
IRQ0
AA6
IOEN
AA7
DMAR0
AA8
HBR
AA9
L3BCMPO
AA10
L3DATO1_N
AA11
L3DATO3_N
AA12
V
SS
AA13
L3DATI2_N
AA14
L3DATI1_N
AA15
NC
AA16
L2DATO0_N
AA17
L2CLKON
AA18
L2DATO3_N
AA19
L2CLKINN
AA20
L2DATI1_N
AA21
V
SS
AA22
L1BCMPO
AA23
L1DATO0_N
AA24
L1DATO0_P
1
On revision 1.x silicon, the R2 and R3 balls are NC. On revision 0.x silicon, the R2 ball is SCLK, and the R3 ball is SCLK_V
on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com).
Ball No. Signal Name
V1
MSSD2
V2
DS2
V3
POR_IN
V4
CONTROLIMP1
V5
V
SS
V6
V
DD
V7
V
DD
V8
V
DD
V9
V
DD
V10
V
DD
V11
V
DD_DRAM
V12
V
DD_DRAM
V13
V
DD
V14
V
DD
V15
V
DD_DRAM
V16
V
DD_DRAM
V17
V
DD
V18
V
DD
V19
V
DD
V20
V
DD_IO
V21
L1DATI3_N
V22
L1DATI3_P
V23
L1DATI2_N
V24
L1DATI2_P
AB1
V
SS
AB2
V
SS
AB3
V
SS
AB4
NC
AB5
IRQ2
AB6
IRQ1
AB7
DMAR1
AB8
HBG
AB9
L3ACKI
AB10
L3DATO1_P
AB11
L3DATO3_P
AB12
V
SS
AB13
L3DATI2_P
AB14
L3DATI1_P
AB15
V
SS
AB16
L2DATO0_P
AB17
L2CLKOP
AB18
L2DATO3_P
AB19
L2CLKINP
AB20
L2DATI1_P
AB21
L2ACKO
AB22
V
SS
AB23
V
DD_IO
AB24
V
DD_IO
Rev. C | Page 44 of 48 | December 2006
Ball No. Signal Name
W1
CONTROLIMP0
W2
ENEDREG
W3
TDI
W4
TDO
W5
V
DD_IO
W6
V
DD
W7
V
DD
W8
V
DD
W9
V
DD
W10
V
DD
W11
V
DD_DRAM
W12
V
DD_DRAM
W13
V
DD
W14
V
DD
W15
V
DD_DRAM
W16
V
DD_DRAM
W17
V
DD
W18
V
DD
W19
V
DD
W20
V
DD_IO
W21
L1CLKON
W22
L1CLKOP
W23
L1DATO3_N
W24
L1DATO3_P
AC1
FLAG0
AC2
V
SS
AC3
V
DD_IO
AC4
TMS
AC5
IOWR
AC6
DMAR2
AC7
CPA
AC8
BOFF
AC9
L3DATO0_N
AC10
L3CLKON
AC11
L3DATO2_N
AC12
L3DATI3_N
AC13
L3CLKINN
AC14
L3DATI0_N
AC15
L3ACKO
AC16
L2BCMPO
AC17
L2DATO1_N
AC18
L2DATO2_N
AC19
L2DATI3_N
AC20
L2DATI2_N
AC21
L2DATI0_N
AC22
V
DD_IO
AC23
V
SS
AC24
L1ACKI
REF
Ball No. Signal Name
Y1
EMU
Y2
TCK
Y3
TMR0E
Y4
FLAG3
Y5
V
SS
Y6
V
DD_IO
Y7
V
SS
Y8
V
DD_IO
Y9
V
SS
Y10
V
DD_IO
Y11
V
DD_IO
Y12
V
DD_IO
Y13
V
DD_IO
Y14
V
DD_IO
Y15
V
DD_IO
Y16
V
SS
Y17
V
DD_IO
Y18
V
SS
Y19
V
DD_IO
Y20
V
SS
Y21
L1DATO1_N
Y22
L1DATO1_P
Y23
L1DATO2_N
Y24
L1DATO2_P
AD1
V
SS
AD2
ID1
AD3
V
DD_IO
AD4
TRST
AD5
IORD
AD6
DMAR3
AD7
DPA
AD8
BUSLOCK
AD9
L3DATO0_P
AD10
L3CLKOP
AD11
L3DATO2_P
AD12
L3DATI3_P
AD13
L3CLKINP
AD14
L3DATI0_P
AD15
L3BCMPI
AD16
L2ACKI
AD17
L2DATO1_P
AD18
L2DATO2_P
AD19
L2DATI3_P
AD20
L2DATI2_P
AD21
L2DATI0_P
AD22
V
DD_IO
AD23
L2BCMPI
AD24
V
SS
. For more information on SCLK and SCLK_V
REF

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