Read GPTCn Registers
Write GPTCn Registers
21.6.7
GPT Toggle-On-Overflow Register (GPTTOV)
IPSBAR
Offset: 0x1A_0008 (GPTTOV)
7
R
0
W
Reset:
0
Field
7–4
Reserved, should be cleared.
3–0
Toggles the output compare pin on overflow for each channel. This feature only takes effect when in output compare
TOV
mode. When set, it takes precedence over forced output compare but not channel 3 override events. These bits are
read anytime, write anytime.
1
Toggle output compare pin on overflow feature enabled
0 Toggle output compare pin on overflow feature disabled
21.6.8
GPT Control Register 1 (GPTCTL1)
IPSBAR
Offset: 0x1A_0009 (GPTCTL1)
7
R
OM3
W
Reset:
0
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
Write GPTFLG1 Register
CnF
TFFCA
Figure 21-8. Fast Clear Flag Logic
6
5
0
0
0
0
Figure 21-9. GPT Toggle-On-Overflow Register (GPTTOV)
Table 21-10. GPTTOV Field Description
6
5
OL3
OM2
0
0
Figure 21-10. GPT Control Register 1 (GPTCTL1)
Data Bit n
4
3
0
0
0
Description
4
3
OL2
OM1
0
0
General Purpose Timer Module (GPT)
Clear
CnF Flag
Access: Supervisor read/write
2
1
TOV
0
0
Access: Supervisor read/write
2
1
OL1
OM0
0
0
0
0
0
OL0
0
21-9