Internal Bus Arbitration; Overview - Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

IPSBAR 0x0013 (CWSR)
Offset:
7
R
W
Reset: Uninitialized
12.6

Internal Bus Arbitration

The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic
that controls which of up to four MBus masters (M0–M3 in
The function of the arbitration logic is described in this section.
12.6.1

Overview

The basic functionality is that of a 2-port, pipelined internal bus arbitration module with the following
attributes:
• The master pointed to by the current arbitration pointer may get on the bus with zero latency if the
address phase is available. All other requesters face at least a one cycle arbitration pipeline delay
to meet bus timing constraints on address phase hold.
• If a requester receives an immediate address phase (that is, it is pointed to by the current arbitration
pointer and the bus address phase is available), it is the current bus master and is ignored by
arbitration. All remaining requesting ports are evaluated by the arbitration algorithm to determine
the next-state arbitration pointer.
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
6 5
Figure 12-5. Core Watchdog Service Register (CWSR)
Figure 12-6. Arbiter Module Functions
Back door to SRAM and flash
SRAM1
MPARK
CPU
M0
DMA
M2
MARB
Internal
Bus
Master
M1
4 3
CWSR[7:0]
Figure 12-6) has access to the external buses.
RAMBAR
Internal
Modules
System Control Module (SCM)
Access: read/write
2 1 0
12-9