Peripheral Power Management Register Low (Ppmrl) - Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

Power Management
8.2.1.1

Peripheral Power Management Register Low (PPMRL)

IPSBAR
Offset: 0x0018 (PPMRL)
31
R 0
W
Reset 0
23
R 0
W
Reset 0
15
R
CDTMR2
W
Reset 0
7
R
CDUART2
W
Reset 0
Figure 8-2. Peripheral Power Management Register Low (PPMRL)
Field
31–18 Reserved, should be cleared.
17 Disable clock to the INTC0 module.
CDINTC0 0 INTC0 module clock is enabled
1 INTC0 module clock is disabled
16 Disable clock to the DTIM3 module.
CDTMR3 0 TMR3 module clock is enabled
1 TMR3 module clock is disabled
15 Disable clock to the DTIM2 module.
CDTMR2 0 TMR2 module clock is enabled
1 TMR2 module clock is disabled
14 Disable clock to the DTIM1 module.
CDTMR1 0 TMR1 module clock is enabled
1 TMR1 module clock is disabled
13 Disable clock to the DTIM0 module.
CDTMR0 0 TMR0 module clock is enabled
1 TMR0 module clock is disabled
12–11 Reserved, should be cleared.
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
8-4
30 29
0 0
0 0
22 21
0 0
0 0
14 13
CDTMR1 CDTMR0
0 0
6 5
CDUART1 CDUART0
0 0
Table 8-3. PPMRL Field Descriptions
28 27
0 0
0 0
20 19
0 0
0 0
12 11
0 0
0 0
4 3
1
CDDMA
0 1
Description
Access: read/write
26 25
0 0
0 0
18 17
0
CDINTC0
0 0
10 9
CDQSPI CDI2C
0 0
2 1
0
CDG
0 0
Freescale Semiconductor
24
0
0
16
CDTMR3
0
8
0
0
0
0
0