Functional Architecture
The system is designed to populate any rank on either channel, including either degenerate
single channel case.
DIMM and memory configurations must adhere to the following:
•
DDR2 667/800, un-buffered, DDR2 DIMM modules
•
DIMM organization: x64 non-ECC or x72 ECC
•
Pin count: 240
•
DIMM capacity: 512 MB, 1 GB and 2 GB DIMMs
•
Serial PD: JEDEC Rev 2.0
•
Voltage options: 1.8 V
•
Interface: SSTL2
Table 10. Memory Bank Labels and DIMM Population Order
Location
28
DIMM Label
J8J1
(DIMM_1A)
J8J2
(DIMM_2A)
J9J1
(DIMM_1B)
J9J2
(DIMM_2B)
Intel® Server Boards S3200SH/S3210SH TPS
Channel
Population Order
A
1
A
3
B
2
B
4
Revision 1.3
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