Table of Contents
Advertisement
Functional Architecture
The device has the following features:
•
Uses PCI 32 bit/33MHz PCI Interface
•
IEEE802.3x compliant flow control support
•
Integrated PHY for full 10/100/1000 Mbps full and half duplex operation
•
On-board Microcontroller
•
Wake-On LAN Support
•
IPMI support for server management
3.10 GigE PHY
The Intel 82566 Gigabit Ethernet physical layer transceiver (PHY) is a single port device that
supports the integrated ICH9 Media Access Controller (MAC) at 10 Mbps, 100 Mbps, or 1000
Mbps.
The PHY is interfaced to the ICH9 using a high-speed serial interface, the Gigabit LAN Connect
Interface (GLCI). This interface operates using two capacitively coupled differential pairs; one
transmit pair and one receive pair.
The PHY is also interfaced to the ICH9 using a lower frequency LAN Connect Interface (LCI).
The LCI interface operates using eight single ended signals, one clock, three transmit, three
receive, and one reset/sync.
The dual interface, GLCI/LCI allows the interfaces to be dynamically controlled based on the
link speed. In gigabit Ethernet mode, the GLCI is used to transmit and receive data and the LCI
is used for Management Data Input/Output (MDIO). For all other link speeds including no-link
and power-down, the GLCI is electrically idle. In states S3 – S5 the gigabit Ethernet link will not
be supported.
3.11 On Board Components
3.11.1
Video Support
The server board includes an integrated VGA graphics engine in Integrated BMC that supports
standard VGA drivers with analog display capabilities. The graphics subsystem has 8 MB
memory to support the onboard video controller. The baseboard provides a standard 15-pin
VGA connector at the rear of the system, in the standard ATX I/O opening area. The video
controller is disabled by default in BIOS Setup when an off-board video adapter is detected in
either the PCIe* or PCI slots.
40
Intel® Server Boards S3200SH/S3210SH TPS
Revision 1.3
Hide quick links:
Advertisement
Table of Contents
