Memory Sub-System; Memory Configuration - Intel S3210SHLX - Entry Server Board Motherboard Specification

Intel® Server Boards S3200SH/S3210SH TPS
The server board provides two external USB ports on the rear panel of the server board. The
dual-stack USB connector is located within the standard ATX I/O panel area. The Universal
Serial Bus Specification, Revision 1.1, defines the external connectors.
The third/fourth USB port is optional and can be accessed by cabling from an internal 9-pin
connector located on the base board to an external USB port located either in front or the rear
of a given chassis.
3.2.3.23 Enhanced Power Management
One of the embedded functions of the Intel
used to implement ACPI-compliant power management features. The server board supports
sleep states S1, S4, and S5.
3.3

Memory Sub-System

The server board supports up to four DIMM slots for a maximum memory capacity of 8 GB. The
DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at
533/667MTs. The memory controller supports the following:
•
Single-bit error correction
•
Multiple-bit error detection
•
Memories using 512Mbit, 1Gbit, 2Gbit DRAM based on memory technology
Memory can be implemented with either single sided (one row) or double-sided (two row)
DIMMs.
3.3.1

Memory Configuration

The memory interface between the MCH and the DIMMs is 72-bit (ECC) wide interface.
There are two banks of DIMMs, labeled 1 and 2. Bank 1 contains DIMM socket locations
DIMM_1A and DIMM_2A. Bank 2 contains DIMM socket locations DIMM_1B and DIMM_2B.
The sockets associated with each bank or "channel," are located next to each other and the
DIMM socket identifiers are marked on the server board silkscreen, near the DIMM socket.
Bank 1 is associated with Memory Channel A while Bank 2 is associated with Memory Channel
B. When only two DIMM modules are being used, the population order must be DIMM_1A,
DIMM_1B to ensure dual channel operating mode.
In order to operate in dual channel dynamic paging mode, the following conditions must be met:
•
Two identical DIMMs are installed, one each in DIMM_1A and DIMM_1B
•
Four identical DIMMs are installed (one in each socket location)
Note: Installing only three DIMMs is not supported. Do not use DIMMs that are not "matched"
(same type and speed). Use of identical memory parts is preferred.
See Figure 7 on the following page for reference.
Revision 1.3
®
ICH9R is a power management controller. This is
Functional Architecture
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