Intel S3210SHLX - Entry Server Board Motherboard Specification page 32

Functional Architecture
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Interface to ICH9R South Bridge
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100 MHz reference clock shared with PCIe* interface(s)
•
PCIe* x8 Interface
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Connected to two PCIe* X8 connectors as shown in the block diagram
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Compliant with the PCIe* base specification
The MCH accepts access requests from the host (processor) bus and directs those accesses to
memory or to one of the PCI Express* or PCI buses. The MCH monitors the host bus,
examining addresses for each request. Accesses may be directed to the following:
•
A memory request queue for subsequent forwarding to the memory subsystem
•
An outbound request queue for subsequent forwarding to one of the PCI Express* or
PCI buses
The MCH also accepts inbound requests from the Intel
generating the appropriate controls to control data transfer to and from memory.
The MCH is a FC-BGA device and uses the proven components of the following previous
generations:
•
Hub interface unit
•
PCI Express* interface unit
•
DDR2 memory interface unit
The MCH incorporates an integrated PCI Express* interface. The PCI Express* interface allows
the MCH to directly interface with the PCI Express* devices. The MCH also increases the main
memory interface bandwidth and maximum memory configuration with a 72-bit wide memory
interface.
The MCH integrates the following main functions:
•
An integrated high performance main memory subsystem
•
A PCI Express* bus which provides an interface to the PCI Express* devices (Fully
compliant to the PCI Express* Base Specification, Rev 1.0a)
•
A DMI which provides an interface to the Intel
Other features provided by the MCH include the following:
•
Full support of ECC on the processor bus
•
Twelve deep in-order queue, two deep defer queue
•
Full support of un-buffered DDR2 ECC DIMMs
•
Support for 512MB, 1GB and 2GB DDR2 memory modules
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Intel® Server Boards S3200SH/S3210SH TPS
®
ICH9R. The MCH is responsible for
®
ICH9R
Revision 1.3