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Functional Architecture
two SPI flash components using two separate chip select pins. Each component may be up to
16 MB and operate in SPI Fast Read Instructions and frequencies of 20 MHZ or 33 MHz.
The SPI Interface consists of the following:
•
Clock (CLK)
•
Master Out Slave In (MOSI)
•
Master In Slave Out (MISO)
•
Chip Select (CS#)
Communication on the SPI is done with a Master – Slave protocol.
The SPI flash may operate in two operational modes, descriptor and non-descriptor. When
operating in non-descriptor mode the SPI Flash can only support BIOS through register
accesses.
When used in descriptor mode the ICH9 allows a single SPI flash device to store system BIOS,
Firmware and Gigabit Ethernet EEPROM information.
When SPI is selected by the Boot BIOS Destination Strap and a SPI Device is detected by the
ICH9, LPC based BIOS Flash is disabled. The boot destination strap is sampled by the ICH9 at
pins GNT# and SPI_CS1# on the rising edge of the PWROK input. Alternately, the ICH9
support soft straps when operating in Descriptor Mode. The ICH9 reads the soft strap data out
of the SPI device prior to de-assertion of reset to the Manageability Engine and the Host
system.
GNT# and SPI_CS1# are both pulled-up with soft resistors internal to the ICH9. The default
BIOS flash without external straps is the FWH. For manufacturing or debug support, the BIOS
cycles may also be directed to the PCI bridge via the same external flash. Configurations other
than the default will be selected via 2.2K pull-up or pull-down resistors.
The server board will support the boot BIOS Destination Selection as defined in table below.
GNT#
SPI_CS1#
0
1
1
24
Table 8 Boot BIOS Destination Selection
1
Flash Cycles Routed to SPI (Default)
0
Flash Cycles Routed to PCI (Test only)
1
Flash Cycles Routed to LPC (Test only)
Intel® Server Boards S3200SH/S3210SH TPS
ROUTING
Revision 1.3
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