Table 4. Segment F Connections; Table 5. Supported Ddr2 Modules - Intel S3210SHLX - Entry Server Board Motherboard Specification

Intel® Server Boards S3200SH/S3210SH TPS
3.2.1.1 Segment F PCIe* x8
The MCH PCIe* Lanes 0~7 provide a x8 PCIe* connection directly to the MCH. This resource
can support x1, x4, and x 8 PCIe* add-in cards or cards through the I/O riser when using the
riser slot for the L board SKU.
Lane
Lane 0~7
3.2.1.2 MCH Memory Sub-System Overview
The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of
DDR2 memory using 2GB DIMMs. This configuration needs external registers for buffering the
memory address and control signals. The four chip selects are registered inside the MCH and
need no external registers for chip selects.
The memory interface runs at 667/800 MT/s. The memory interface supports a 72-bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 512MB,
1GB, and 2GB DRAM densities. The DDR DIMM interface supports single-bit error correction,
and multiple bit error detection.
3.2.1.3 DDR2 Configurations
The DDR2 interface supports up to 8GB of main memory and supports single- and double-
density DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the
DDR2 DIMM technology supported.
DIMM DIMM
Capacity Organization
512MB 64M x 72
512MB 64M x 72
1GB 128M x 72
1GB 128M x 72
2GB 256M x 72
3.2.1.4 Memory Population Rules and Configurations
There are a few rules that must be followed when populating memory. The server board
supports two DDR2 DIMM slots for channel A, and two DDR2 DIMM slots for channel B. They
are placed in a row and numbered from 0 to 3 with DIMM0 being closest to the MCH. The four
slots are partitioned with channel A representing the channel A DIMMs (DIMM0 and DIMM1)
and channel B representing the channel B DIMMs (DIMM2 and DIMM3).
Revision 1.3

Table 4. Segment F Connections

Slot 6 (PCI Express* x16 with 8 Lanes layout)

Table 5. Supported DDR2 Modules

DDR2-667/800 Un-buffered
SDRAM Module Matrix
SDRAM SDRAM
Density Organization
256Mbit 32M x 8
512Mbit 64M x 8
512Mbit 64M x 8
1Gbit 128M x 8
2GB 128M x 8
Functional Architecture
Device
# SDRAM
Devices/rows/Banks
18 / 2 / 4 13 / 2 / 10
9 / 1 / 4 14 / 2 / 10
18 / 2 / 4 14 / 2 / 10
9 / 1 / 8 14 / 4 / 10
18 / 2 / 8 14 / 8 / 10
# Address bits
rows/Banks/column
19