Error Logging Via Smi Handler; Smbios Type 15; Logging Format Conventions - Intel S3210SHLX - Entry Server Board Motherboard Specification

Intel® Server Boards S3200SH/S3210SH TPS
PCI PERR error
PCI SERR error
5.1.2

Error Logging via SMI Handler

The SMI handler is used to handle and log system level events. The SMI handler pre-processes
all system errors, even those that are normally considered to generate an NMI.
The SMI handler logs the event to NVRAM. For example, the BIOS programs the hardware to
generate SMI on a single-bit memory error and logs the error in the NVRAM in the terms of
SMBIOS Type 15. After the BIOS finishes logging the error it will assert the NMI if needed.
5.1.2.1 PCI Bus Error
The PCI bus defines two error pins, PERR# and SERR#. These are used for reporting PCI
parity errors and system errors, respectively.
In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to
report it using SERR#. All other PCI-related errors are reported by SERR#. All PCI-to-PCI
bridges are configured so that they generate SERR# on the primary interface whenever there is
SERR# on the secondary side. The format of the data bytes is described in Section 5.1.4
5.1.2.2 PCI Express* Errors
All uncorrectable PCI Express* errors are logged as PCI system errors and promoted to an NMI.
All correctable PCI Express* errors are logged as PCI parity errors.
5.1.2.3 Memory Errors
The hardware is programmed to generate an SMI on correctable data errors in the memory
array. The SMI handler records the error to the NVRAM. The uncorrectable errors may have
corrupted the contents of SMRAM. The SMI handler will log the error to the NVRAM if the
SMRAM contents are still valid. The format of the data bytes is described in Section 5.1.4
5.1.3

SMBIOS Type 15

Errors are logged to NVRAM in the terms of SMBIOS Type 15 (System Event Log). Please refer
to the SMBIOS Specification, version 2.4 for more detail information. The format of the records
is also defined in following section.
5.1.4

Logging Format Conventions

BIOS logs an error into the NVRAM area with the following record format, which is also defined
in the SMBIOS Specification, version 2.4.
Revision 1.3
Code.
PERR error happens on PCI bus
SERR error happens on PCI bus
Error Reporting and Handling
POST / Runtime
POST / Runtime
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