Clock Generator; Super I/O; Gige Controller 82541Pi - Intel S3210SHLX - Entry Server Board Motherboard Specification

Intel® Server Boards S3200SH/S3210SH TPS
The Intel 6702PXH 64-bit PCI Hub further support the new PCI Standard Hot-Plug
Controller and Subsystem Specification, Revision 1.0. Each PCI interface contains an
I/OxAPIC with 24 interrupts and a standard hot plug controller.
3.7

Clock Generator

CK505 compliant Clock Synthesizer chip solution is used to generate most of the required
clocks on the Snow Hill Server board. The CK505 synthesizes and distributes a multitude of
clock outputs at various frequencies, timings and drive levels using a single parallel resonance
14.31818 MHz (50ppm or less) crystal.
The CK505 clock generator supplies host clocks (at 200-MHz, 266-MHz and 333MHz), 100-
MHz clocks, 48-MHz clocks, 33-MHz clocks and 14-MHz clocks.
The CK505 has 12 SRC outputs targeted for PCIe* applications at 100MHz.
CK505 is the main clock source for the entire system.
•
The clock generator is configured to support the following number of clocks.
−
Differential host clock pairs for processor, MCH and XDP
−
Differential 100 MHz to ICH9 (DMI & SATA), MCH, XDP, and PCIe* slots
−
33-MHz clocks for ICH9, SIO, SM712,, Port 80/81h and PCI32 slots
−
Single ended 48-MHz clock for the ICH9 USB Controller
−
Single ended 14.318-MHz clocks shared between the ICH9 and SIO
−
Debug jumpers to manually select FSB/host clock frequency
•
SMBus interface for spread spectrum support.
•
Option to retain register contents in PWRDWN# state.
3.8

Super I/O

The super I/O is a Winbond* PC8374L super I/O located on the ICH9 LPC bus. This device has
the following features utilized on the Snow Hill:
•
LPC rev 1.1
•
Floppy Disk Controller with a Digital Data Separator
•
KB and Mouse Controller (KBC)
•
ACPI 2.0b Compliant
•
Sensor Path* Interface
3.9

GigE Controller 82541PI

®
The Intel 82541 Gigabit Ethernet Controller is a single, compact component with integrated
Gigabit Ethernet Media Access Controller (MAC) and Physical Layer (PHY) function. This
device is interfaced to the ICH9 using PCI 32 bit/33MHz. The server board uses this device
along with the integrated ICH9 MAC and external 82566 PHY to provide two Gigabit Ethernet
Ports.
Revision 1.3
Functional Architecture
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