Block Diagram; Figure 1 - Module Functional Block Diagram - ADLINK Technology AMD COM Express Express-VR7 User Manual

Express-VR7 User's Guide

3. Block Diagram

USB 2.0 Lane 0-3
4x GPI Interrupt
Page 19
PCIe Lane 0-3
x4, x2, x1 (four controller)
PCIe Lane 4-5 GEN4
x2 (one controller)
SATA Port 0-1
Up to 2.5GbE
i226
NCSI
BIOS
TPM
BIOS
SPI
GP_SPI (OEM)
SMBus
I2C
I2C
UART 0-1
2x UART
4x GPI
4x GPO
4x GPO
eSPI to LPC
Bridge IC
Embedded Controller
IPMB
MMC
LPC/eSPI
Figure 1 – Module functional block diagram
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GEN4
AMD Embedded
Ryzen V3000
eSPI
DDR5
SODIMM
Thermal
sensor
ECC/non-ECC
(TBC)
SODIMM
Thermal
sensor ECC/non-ECC
(board)
GEN4 PCIe Lane 16-23
x8, x4 (two controller)
USB 3.x Lane 0-3
(high speed lanes)
10G_SDP 0-1
10G_SDP 2-3
10G_KR 0-1 &
sideband signals
(additional
MDIO/MDC, OEM)
DDR5
PICMG COM.0 R3.1