Block Diagram; Figure 1 - Module Function Block Diagram - ADLINK Technology arm AMPERE COM-HPC-ALT User Manual

COM-HPC-ALT User's Guide

3. Block Diagram

GROUP 0 Low
GROUP 0 High
Page 20
J1
1 x4, 2 x2
PCIe Lane 0-3
1 x4, 2 x2
PCIe Lane 4-7
2 x2, 1 x4
PCIe Lane 8-11
2 x2, 1 x4
PCIe Lane 12-15
(Root Complex B)
PCIe_BMC x1
can be x8
ETH_KR 0-3 PCIe x8
BCM57502
ETH_KR 4-7
4x USB 3.x/2.0 0-3
PCIe x1
uPD720201
4x USB 2.0 4-7
SATA Port 0-1
NBASE-T 0
LAN
Intel i210
BIOS
BOOT_SPI
TPM
GPP_SPI
SMBus
I2C_9
EEPROM
I2C 0
(w/ ALERT#)
I2C 1
HSUART
UART 0
HSUART
UART 1
UART_1 RTS#, CTS# simulated by GPIO
HSUART
GPIO x12
USB_PD_
MMC
IPMB
ATMEGA
Sensor for monitoring
Discrete
voltage/current/temp
eSPI
(power
sequence)
Note:
-All the PCIe are Gen4
-I2C_9 from Altra SOC supports CCIX mode code (ready now) or general purpose SMBUS mode code (TBC), either one
-UART_1: TX, RX come from SOC, RTS#, CTS# are simulated by SOC GPIO
-USB_PD_I2C, MMC, SOC: connect together
-need work with AST2500 Remote BMC on carrier
Figure 1 – Module Function Block Diagram
Copyright © 2023 ADLINK Technology, Inc.
1 x16, 2 x8, 4 x4
(Root Complex B) (Root Complex A)
1 x16, 2 x8, 4 x4
(Root Complex A)
can be x8
1 x16, 2 x8, 4 x4
(Root Complex A)
Ampere Computing
Altra
DIMM DIMM DIMM
3200 MT/s 3200 MT/s 3200 MT/s
DIMM DIMM DIMM
3200 MT/s 3200 MT/s 3200 MT/s
PICMG COM-HPC R1.0
J2
PCIe Lane 16-31
GROUP 1
PCIe Lane 32-47
GROUP 2
PCIe Lane 48-63
GROUP 3
ETH_Sidebands
Rapid Shutdown