Ipmb (Optional) - ADLINK Technology AMD COM Express Express-VR7 User Manual

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Express-VR7 User's Guide

Note: SER0, SER1 source from EC is default setting. SER0, SER1 source from SoC's HSUART is by build option by supported by project basis.

HSUART has driver support limitation.

4.3.13 IPMB (Optional)

Name

Pin #

Description

IPMB_CLK

A32

Clock I/O line for the multi-master IPMB port. If the

IPMB interface is used, an additional lower value pull-up

is located on the Carrier.

IPMB_DAT

A33

Data I/O line for the multi-master IPMB port. If the IPMB

interface is used, an additional lower value pull-up is

located on the Carrier.

Note: IPMB via a Module MMC is supported by project basis and it is still in development (TBC)

Page 39

I/O

I/O OD

3.3VSB

I/O OD

3.3VSB

PU / PD

Comment

PU 47K

3.3VSB

PU 47K

3.3VSB

PICMG COM.0 R3.1

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