ADLINK Technology AMD COM Express Express-VR7 User Manual page 24

Express-VR7 User's Guide
Row A
A106 VCC_12V
A107 VCC_12V
A108 VCC_12V
A109 VCC_12V
A110 GND (fixed)
Note:
1. 10G SFP+ or 10GBASE-T support is based on CEI mode (sideband signal arrangement related) and requires PHY (CS4227 or AQR113C) along
with on-carrier firmware, for SFP+ or 10GBASE-T applications. A reference design will be offered. Please contact our ADLINK representative
for availability.
2. Another PCIe clock (PCIE_CK_REF1) defined by PICMG COM.0 R3.1 can be used for PCIe lane 16-23. Check pin B29, B30.
3. Features listed below are supported by project basis (1) IPMB function (2) GBE0_SDP with specific LAN controller (3) 10G_SDP 0-3. (4) GP_SPI,
general purpose SPI. (5) Additional MDC/MDIO (10G_PHY_MDC_SCL1, 10G_PHY_MDIO_SDA1). All these project basis support features are still
in development stage.
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Row B
B106 VCC_12V
B107 VCC_12V
B108 VCC_12V
B109 VCC_12V
B110 GND (FIXED)
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Row C
C106 VCC_12V
C107 VCC_12V
C108 VCC_12V
C109 VCC_12V
C110 GND (FIXED)
PICMG COM.0 R3.1
Row D
D106 VCC_12V
D107 VCC_12V
D108 VCC_12V
D109 VCC_12V
D110 GND (FIXED)