Expansion Buses - ADLINK Technology AMD COM Express Express-VR7 User Manual

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Express-VR7 User's Guide

Embedded BIOS

AMI Aptio V UEFI with CMOS backup in 32 MB SPI BIOS, dual BIOS by build option

2.2. Expansion Buses

8 PCI Express Gen4: Lane 16-23 (two controllers, configurable to 1 x8 or 2 x4)

PCIe reference clock can be PCIE_CK_REF1 (pin B29/B30) or PCIE_CK_REF (pin A88/A89). PCIE_CK_REF1 recommended

4 PCI Express Gen4: Lanes 0-3 (four controllers, configurable to 1 x4, 2 x2/x1) (4 x1 usage supported but requires prior inquiries)

2 PCI Express Gen4: Lane 4-5 (one controller only, configurable to 1 x2/x1)

Note: Preferred Link Configuration on PCIE 0-3 defined by PICMG is 1 x4 or 1 x2 or 1 x1. PCIe Gen4 support also depends on carrier board design

Other: SMBus (system), I

C (user), LPC bus (via eSPI to LPC bridge IC).

C from CPU is supported by BOM option and project basis

SMBus from EC (embedded controller) is supported by BOM option and project basis

Additional GP_SPI (general purpose SPI by project basis)

Page 13

PICMG COM.0 R3.1

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