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Infineon TLE9845QX Manuals
Manuals and User Guides for Infineon TLE9845QX. We have
1
Infineon TLE9845QX manual available for free PDF download: User Manual
Infineon TLE9845QX User Manual (972 pages)
Microcontroller with LIN and Power Switches for Automotive Applications
Brand:
Infineon
| Category:
Microcontrollers
| Size: 22.73 MB
Table of Contents
Table of Contents
2
1 Overview
14
Tle984Xqx Product Variants
15
Abbreviations
16
2 Block Diagram
18
3 Device Pinout and Pin Configuration
19
Device Pinout
19
Pin Configuration
20
4 Modes of Operation
23
5 Device Register Types
26
6 Power Management Unit (PMU)
28
Features
28
Introduction
28
Block Diagram
29
PMU Modes Overview
31
Power Supply Generation
37
Voltage Regulator 5.0V (VDDP)
37
Voltage Regulator 1.5V (VDDC)
39
External Voltage Regulator 5.0V (VDDEXT)
40
Power-On Reset Concept
41
PMU Register Overview
42
Register Definition
42
Power Supply Generation Register
42
VDDEXT Control Register
46
Power Control Unit
48
Power Control Unit - Fail Safe Scenarios
48
Power Supervision Function of PCU
48
Watchdog (WDT1) Fail Safe
49
Main Regulators Fail Safe
49
VDDEXT Failure
49
Wake-Up from Stop Mode with Reset Fail Safe
49
Register Definition
51
Wake-Up Management Unit (WMU)
53
Register Definition
55
PMU Wake up Configuration Register
56
PMU Wake up Status Register
60
GPIO Port Wake up Status Register
63
Cyclic Management Unit (CMU)
65
Cyclic Sense Mode
65
Configuration of Cyclic Sense Mode
66
Cyclic Wake Mode
68
Register Definition
68
Cyclic Mode Configuration Registers (CYCMU)
69
Reset Management Unit (RMU)
72
Register Definition
75
Reset Management Unit Registers (RMU)
76
PMU Data Storage Area
80
Register Definition
80
Data Storage Registers
80
7 System Control Unit - Digital Modules (SCU-DM)
83
Features
83
Introduction
83
Block Diagram
84
SCU Register Overview
86
Register Map
86
Clock Generation Unit
89
Low Precision Clock
89
High Precision Oscillator Circuit (OSC_HP)
90
External Input Clock Mode
90
External Crystal Mode
90
Phase-Locked Loop (PLL) Module
91
Features
91
PLL Functional Description
91
Oscillator Watchdog
96
PLL VCO Lock Detection
97
Internal Oscillator (OSC_PLL)
97
Switching PLL Parameters
97
Oscillator Watchdog Event or PLL Loss of Lock Detection
98
Oscillator Watchdog Event or Loss of Lock Recovery
98
Clock Control Unit
100
Clock Tree
102
Startup Control for System Clock
103
External Clock Output
103
CGU Registers
104
PLL Oscillator Register
104
PLL Registers
106
System Clock Control Registers
112
Analog Peripherals Clock Control Registers
114
External Clock Control Register
122
Reset Control
124
Types of Reset
124
Overview
124
Module Reset Behavior
124
Functional Description of Reset Types
126
Power-On / Brown-Out Reset
126
Wake-Up Reset
126
Hardware Reset
126
WDT1 Reset
126
Soft Reset
126
Reset Register Description
127
Booting Scheme
128
Power Management
129
Overview
129
Functional Description
130
Slow down Mode
130
Stop Mode
130
Sleep Mode
132
Register Description
133
Interrupt Management
135
Overview
135
External Interrupts
135
Extended Interrupts
136
Interrupt Node Assignment
136
Interrupt Registers
138
Interrupt Node Enable Registers
139
External Interrupt Control Registers
143
Interrupt Flag Registers
146
Interrupt Related Registers
170
Interrupt Event Enable Control
170
NMI Event Flags Handling
177
General Port Control
178
Input Pin Function Selection
178
Port Output Control
185
GPT12 T3IN/T4IN Input Pin Function Selection
191
Differential Unit Trigger Enable (Only TLE9845QX)
192
Differential Unit Trigger
192
Differential Unit Trigger Register
192
Flexible Peripheral Management
195
Peripheral Management Registers
196
Module Suspend Control
198
Baud-Rate Generator
200
Baudrate Generator Registers
200
Baud-Rate Generator Control and Status Registers
200
Baud-Rate Generator Timer/Reload Registers
202
LIN Break and Sync Byte Detection
207
LIN Break and Sync Byte Detection Control
207
LIN Break and Sync Byte Registers
207
Error Detection and Correction Control for Memories
209
Error Detection and Correction Control Register
210
Error Detection and Correction Status Register
211
Miscellaneous Control
214
Bit Protection Register
214
System Control and Status Registers
215
8 System Control Unit - Power Modules (SCU-PM)
225
Description of the Power Modules System Control Unit
225
Introduction
225
Block Diagram
225
Clock Watchdog Unit (CWU)
226
Fail Safe Functionality of Clock Generation Unit (Clock Watchdog)
226
Functional Description of Clock Watchdog Module
227
Clock Generation Unit Register
228
Interrupt Control Unit (ICU)
231
Structure of PREWARN_SUP_NMI
231
Interrupt Control Unit Status Register
233
Interrupt Control Unit Status Overview Register
233
Interrupt Control Unit - Interrupt Clear Register
239
Interrupt Control Unit - Interrupt Enable Register
243
Power Control Unit for Power Modules (PCU_PM)
245
Overtemperature System Shutdown
246
Power Control Unit Register
248
9 Arm® Cortex®-M0 Core
250
Features
250
Introduction
251
Block Diagram
251
Functional Description
251
Registers
252
General-Purpose Registers
252
Special-Purpose Registers
252
Summary of Processor Registers
254
Instruction Set Summary
282
10 Address Space Organization
285
11 Memory Control Unit
289
Features
289
Introduction
289
Block Diagram
289
NVM Module (Flash Memory)
291
Bootrom Module
291
Bootrom Addressing
291
Bootrom Firmware Program Structure
291
RAM Module
292
RAM Addressing
292
Memory Protection Unit (MPU)
293
Memory Protection Regions
293
Hardware Protection Mode
293
Bootrom Protection Mode
294
NVM Protection Modes
295
Firmware Protection Mode
300
Core Protection Mode
302
12 NVM Module (Flash Memory)
303
Definitions
305
General Definitions
305
Functional Description
307
Basic Block Functions
307
Memory Cell Array
308
SFR Accesses
309
Memory Read
309
Memory Write
310
Timing
310
Verify
310
Tearing-Safe Programming
310
Dynamic Address Scrambling
311
Linearly Mapped Sectors
311
Disturb Handling
311
Hot Spot Distribution
312
Properties of Error Correcting Code (ECC)
312
Resume from Disturbed Program/Erase Operation
312
Code and Data Access through the AHB-Lite Interface
313
13 Interrupt System
314
Features
314
Introduction
314
Overview
314
Functional Description
316
Interrupt Node Assignment
316
Interrupt Node 0 and 1 - GPT12 Timer Module
316
Interrupt Node 2 - Measurement Unit
317
Interrupt Node 3 - ADC10
318
Interrupt Node 4, 5, 6, 7 - CCU6
319
Interrupt Node 8 and 9 - SSC
320
Interrupt Node 10 - UART1
321
Interrupt Node 11 - UART2
322
Interrupt Node 12 and 13 - Interrupt
323
Interrupt Node 17 and 18 - LS1, LS2
324
Interrupt Node 19 and 20 - HS1, HS2
325
Interrupt Node 21 - DPP1
326
Interrupt Node 22 - MON1
327
Interrupt Node 23 - Port2.X
328
Non-Maskable Interrupt Request Source (NMI)
329
Interrupt Flags Overview
330
Interrupt Structure 1
337
Interrupt Source and Vector
338
Interrupt Priority
341
Interrupt Handling
342
Interrupt Registers
343
Interrupt Node Enable Registers
344
External Interrupt Control Registers
346
Interrupt Flag Registers
349
Interrupt Priority Registers
374
14 Watchdog Timer (WDT1)
375
Features
375
Introduction
376
Functional Description
376
Modes of Operation
376
Normal Operation
377
Watchdog Register Overview
379
15 GPIO Ports and Peripheral I/O
381
Features
381
Introduction
381
Port 0 and Port 1
382
Port 2
384
General Port Register Description
384
Port Data Register
386
Direction Register
387
Open Drain Control Register
389
Pull-Up/Pull-Down Device Register
390
Alternate Input Functions
394
Alternate Output Functions
394
Port Output Control
396
Tle984Xqx Port Implementation Details
398
Port 0
398
Overview
398
Port 0 Functions
398
Port 0 Register Description
401
Port 1
412
Overview
412
Port 1 Functions
412
Port 1 Register Description
415
Port 2
425
Overview
425
Port 2 Functions
425
Port 2 Register Description
428
16 General Purpose Timer Units (GPT12)
433
Features
433
Features Block GPT1
433
Features Block GPT2
433
Introduction
433
Block Diagram GPT1
434
Block Diagram GPT2
435
Timer Block GPT1
436
GPT1 Core Timer T3 Control
437
GPT1 Core Timer T3 Operating Modes
439
GPT1 Auxiliary Timers T2/T4 Control
445
GPT1 Auxiliary Timers T2/T4 Operating Modes
446
GPT1 Clock Signal Control
453
Interrupt Control for GPT1 Timers
455
GPT12 Registers
456
GPT1 Registers
456
GPT1 Timer Registers
456
GPT1 Core Timer T3 Control Register
458
GPT1 Auxiliary Timers T2/T4 Control Registers
461
Encoding
464
GPT1 Timer Interrupt Control Registers
466
Timer Block GPT2
467
GPT2 Core Timer T6 Control
468
GPT2 Core Timer T6 Operating Modes
469
GPT2 Auxiliary Timer T5 Control
472
GPT2 Auxiliary Timer T5 Operating Modes
473
GPT2 Register CAPREL Operating Modes
476
GPT2 Clock Signal Control
481
Interrupt Control for GPT2 Timers and CAPREL
482
GPT2 Registers
483
GPT2 Timer Registers
483
GPT2 Timer Control Registers
484
Encoding
488
GPT2 Timer and CAPREL Interrupt Control Registers
489
Miscellaneous GPT12 Registers
490
Implementation of the GPT12 Module
493
Module Connections
493
17 Timer2 and Timer21
496
Features
496
Introduction
496
Timer2 and Timer21 Modes Overview
496
Functional Description
497
Auto-Reload Mode
497
Up/Down Count Disabled
498
Up/Down Count Enabled
499
Capture Mode
500
Count Clock
500
Interrupt Generation
501
Timer 2 Register Definition
501
Mode Register
502
Control Register
504
Timer 2 Reload/Capture Register
507
Timer 2 Count Register
508
Timer2 and Timer21 Implementation Details
509
Interfaces of the Timer2 and Timer21
509
18 Capture/Compare Unit 6 (CCU6)
511
Feature Set Overview
511
Introduction
512
Block Diagram
512
Operating Timer T12
514
T12 Overview
515
T12 Counting Scheme
517
Clock Selection
517
Edge-Aligned / Center-Aligned Mode
518
Single-Shot Mode
520
T12 Compare Mode
521
Compare Channels
521
Channel State Bits
521
Hysteresis-Like Control Mode
526
Compare Mode Output Path
527
Dead-Time Generation
527
State Selection
529
Output Modulation and Level Selection
530
T12 Capture Modes
532
T12 Shadow Register Transfer
536
Timer T12 Operating Mode Selection
537
Operating Timer T13
537
T13 Overview
538
T13 Counting Scheme
540
Clock Selection
540
T13 Counting
541
Single-Shot Mode
541
Synchronization to T12
542
T13 Compare Mode
544
Compare Mode Output Path
546
T13 Shadow Register Transfer
547
Trap Handling
549
Multi-Channel Mode
551
Hall Sensor Mode
553
Hall Pattern Evaluation
554
Hall Pattern Compare Logic
556
Hall Mode Flags
556
Hall Mode for Brushless DC-Motor Control
558
Interrupt Handling
560
Interrupt Structure
560
General Module Operation
562
Input Selection
562
CCU6 Register Description
563
System Registers
564
Timer 12 - Related Registers
567
Timer 13 - Related Registers
579
Capture/Compare Control Registers
582
Global Modulation Control Registers
596
Multi-Channel Modulation Control Registers
602
Interrupt Control Registers
608
Tle984Xqx Module Implementation Details
620
Interfaces of the CCU6 Module
620
19 Uart1/Uart2
622
Features
622
Introduction
622
Block Diagram
623
UART Modes
623
Mode 0, 8-Bit Shift Register, Fixed Baud Rate
623
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