Quectel SG865W Series Hardware Design page 67

PCIE2_TX0_P
PCIE2_TX0_M
PCIE2_RX0_P
PCIE2_RX0_M
PCIE2_TX1_P
PCIE2_TX1_M
PCIE2_RX1_P
PCIE2_RX1_M
PCIE2_WAKE_N
PCIE2_RST_N
PCIE2_CLKREQ_N
The following figure illustrates the PCIe interface connection.
PCIE1_TX1_P
PCIE1_TX1_M
PCIE1_RX1_P
PCIE1_RX1_M
PCIE1_REFCLK_P
PCIE1_REFCLK_M
PCIE1_TX0_P
PCIE1_TX0_M
PCIE1_RX0_P
PCIE1_RX0_M
PCIE1_WAKE_N
PCIE1_CLKREQ_N
PCIE1_RST_N
Module
SG865W_Series_Hardware_Design
388 DO
389 DO
391 DI
392 DI
390 DO
394 DO
393 DI
398 DI
370 DI
404 DO
399 DI
C1
C2
C5
C6
R1 R2
1k 10k
VREG_S4A_1V8
Figure 19: Reference Design of PCIe1 Interfaces
PCIe2 transmit 0 (+)
PCIe2 transmit 0 (-)
PCIe2 receive 0 (+)
PCIe2 receive 0 (-)
PCIe2 transmit 1 (+)
PCIe2 transmit 1 (-)
PCIe2 receive 1 (+)
PCIe2 receive 1 (-)
PCIe2 wake up host
PCIe2 reset
PCIe2 clock request
C3
C4
C7
C8
R3
10k
Smart Module Series
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
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