Quectel SG865W Series Hardware Design page 35

CSI5_LN0_N 351
CSI5_LN1_P 346
CSI5_LN1_N 345
CSI5_LN2_P 340
CSI5_LN2_N 339
CSI5_LN3_P 334
CSI5_LN3_N 333
CAM0_MCLK 118
CAM1_MCLK 112
CAM2_MCLK 107
CAM3_MCLK 99
CAM4_MCLK 96
CAM5_MCLK 108
CAM6_MCLK 100
CAM0_RST 119
CAM1_RST 114
CAM2_RST 109
CAM3_RST 103
CAM4_RST 115
CAM5_RST 110
CAM6_RST 104
CCI0_I2C_SDA 151
CCI0_I2C_SCL 157
SG865W_Series_Hardware_Design
MIPI lane 0 data of
AI
camera 5 (-)
MIPI lane 1 data of
AI
camera 5 (+)
MIPI lane 1 data of
AI
camera 5 (-)
MIPI lane 2 data of
AI
camera 5 (+)
MIPI lane 2 data of
AI
camera 5 (-)
MIPI lane 3 data of
AI
camera 5 (+)
MIPI lane 3 data of
AI
camera 5 (-)
Master clock of
DO
camera 0
Master clock of
DO
camera 1
Master clock of
DO
camera 2
Master clock of
DO
camera 3
Master clock of
DO
camera 4
Master clock of
DO
camera 5
Master clock of
DO
camera 6
DO Reset of camera 0
DO Reset of camera 1
DO Reset of camera 2
DO Reset of camera 3
DO Reset of camera 4
DO Reset of camera 5
DO Reset of camera 6
OD I2C data of CCI0
OD I2C clock of CCI0
Smart Module Series
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