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Quectel Smart LTE Module Series Hardware Design

Quectel Smart LTE Module Series Hardware Design

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SC650T
Design
Smart LTE Module Series
Rev: SC650T_Hardware_Design_V1.1
Date: 2019-03-01
Status: Preliminary
Hardware
www.quectel.com

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Summary of Contents for Quectel Smart LTE Module Series

  • Page 1 SC650T Hardware Design Smart LTE Module Series Rev: SC650T_Hardware_Design_V1.1 Date: 2019-03-01 Status: Preliminary www.quectel.com...
  • Page 2 QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION.

  • Page 3: About The Document

    Smart LTE Module Series SC650T Hardware Design About the Document History Revision Date Author Description 2019-02-26 Arsene Initial SC650T_Hardware_Design 2 / 131...

  • Page 4: Table Of Contents

    Smart LTE Module Series SC650T Hardware Design Contents About the Document ..........................2 Contents ..............................3 Table Index ............................... 6 Figure Index .............................. 8 Introduction ............................. 13 1.1. Safety Information ........................14 Product Concept ..........................15 2.1. General Description ........................ 15 2.2.
  • Page 5 Smart LTE Module Series SC650T Hardware Design 3.21.2. Flashlight Interfaces ..................... 73 3.22. Sensor Interfaces ........................74 3.23. Audio Interfaces ........................74 3.23.1. Reference Circuit Design for Microphone Interfaces ........... 76 3.23.2. Reference Circuit Design for Earpiece Interface ............77 3.23.3.
  • Page 6 Smart LTE Module Series SC650T Hardware Design Storage, Manufacturing and Packaging ..................106 9.1. Storage ..........................106 9.2. Manufacturing and Soldering ....................107 9.3. Packaging ..........................108 10 Appendix A References ........................ 110 SC650T_Hardware_Design 5 / 131...
  • Page 7 Smart LTE Module Series SC650T Hardware Design Table Index TABLE 1: SC650T-NA FREQUENCY BANDS ....................15 TABLE 2: SC650T-EM FREQUENCY BANDS ....................15 TABLE 3: SC650T KEY FEATURES ......................... 16 TABLE 4: I/O PARAMETERS DEFINITION ....................... 22 TABLE 5: PIN DESCRIPTION ........................... 22 TABLE 6: POWER DESCRIPTION ........................
  • Page 8 Smart LTE Module Series SC650T Hardware Design TABLE 42: SC650T MODULE POWER SUPPLY RATINGS ................96 TABLE 43: OPERATION AND STORAGE TEMPERATURES ................97 TABLE 44: SC650T-NA CURRENT CONSUMPTION ..................98 TABLE 45: SC650T-EM CURRENT CONSUMPTION ..................98 TABLE 46: SC650T-NA RF OUTPUT POWER ....................99 TABLE 47: SC650T-EM RF OUTPUT POWER ....................
  • Page 9 Smart LTE Module Series SC650T Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ....................... 18 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) ....................21 FIGURE 3: VOLTAGE DROP SAMPLE ......................39 FIGURE 4: STAR STRUCTURE OF POWER SUPPLY ..................40 FIGURE 5: REFERENCE CIRCUIT OF POWER SUPPLY ................40 FIGURE 6: TURN ON THE MODULE USING DRIVING CIRCUIT ..............
  • Page 10 Smart LTE Module Series SC650T Hardware Design GROUND) ..............................90 FIGURE 39: REFERENCE CIRCUIT DESIGN FOR WI-FI/BT ANTENNA INTERFACE ........91 FIGURE 40: REFERENCE CIRCUIT DESIGN FOR GNSS PASSIVE ANTENNA ........... 92 FIGURE 41: REFERENCE CIRCUIT DESIGN FOR GNSS ACTIVE ANTENNA ..........93 FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ..........
  • Page 11 Smart LTE Module Series SC650T Hardware Design OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b).
  • Page 12 Smart LTE Module Series SC650T Hardware Design be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: - Reorient or relocate the receiving antenna. - Increase the separation between the equipment and receiver.
  • Page 13 Smart LTE Module Series SC650T Hardware Design point à point et non point à point, selon le cas CAN ICES-3(B)/ NMB-3(B) Radiation Exposure Statement This equipment complies with FCC/IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &...

  • Page 14: Introduction

    Smart LTE Module Series SC650T Hardware Design Introduction This document defines the SC650T module and describes its air interface and hardware interface which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details as well as other related information of SC650T module.

  • Page 15: Safety Information

    SC650T module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 16: Product Concept

    Smart LTE Module Series SC650T Hardware Design Product Concept 2.1. General Description SC650T is a series of Smart LTE module based on Qualcomm platform and Android operating system, and provides industrial grade performance. Its general features are listed below: ...

  • Page 17: Key Features

    Smart LTE Module Series SC650T Hardware Design LTE-FDD B1/B3/B7/B20/B28 Wi-Fi 802.11a/b/g/n/ac 2402MHz~2482MHz; 5180MHz~5825MHz BT4.2 LE 2402MHz~2480MHz GPS: 1575.42MHz± 1.023MHz GNSS GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz± 2.046MHz SC650T is an SMD type module which can be embedded into applications through its 323 pins (including 152 LCC pads and 171 LGA pads).
  • Page 18 Smart LTE Module Series SC650T Hardware Design  Cat 4 FDD: Max 150Mbps (DL)/Max 50Mbps (UL) 2.4GHz/5GHz, support 802.11a/b/g/n/ac, maximally up to 433Mbps WLAN Features Support AP and STA mode Bluetooth Features BT4.2 LE GNSS Features GPS/GLONASS/BeiDou Text and PDU mode...
  • Page 19 Smart LTE Module Series SC650T Hardware Design Support Dual SIM Dual Standby (supported by default) I2C Interfaces Five I2C interfaces, used for peripherals such as TP, camera, sensor, etc. I2S Interface Support for I2S peripherals 2 high current Flash and torch LED driver ...

  • Page 20: Evaluation Board

    SC650T Hardware Design 2.3. Evaluation Board In order to help customers develop applications with SC650T conveniently, Quectel supplies the evaluation board, USB to RS232 converter cable, USB Type-C data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document [1].

  • Page 21: Application Interfaces

    Smart LTE Module Series SC650T Hardware Design Application Interfaces 3.1. General Description SC650T is equipped with 323-pin 1.0mm pitch SMT pads that can be embedded into cellular application platform. The following chapters provide the detailed description of pins/interfaces listed below.

  • Page 22: Pin Assignment

    Smart LTE Module Series SC650T Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of SC650T module. Figure 1: Pin Assignment (Top View) SC650T_Hardware_Design 21 / 131...

  • Page 23: Pin Description

    Smart LTE Module Series SC650T Hardware Design 3.3. Pin Description Table 4: I/O Parameters Definition Type Description Bidirectional Digital input Digital output Power input Power output Analog input Analog output Open drain The following tables show the SC650T’s pin definition and electrical characteristics.
  • Page 24 Smart LTE Module Series SC650T Hardware Design module. Vmin=3.55V interface Vnorm=3.8V Power supply for max=3.2V VRTC PI/PO internal RTC circuit =2.0V~3.25V Power supply for external GPIO’s pull 1.8V output power Vnorm=1.8V LDO5_1P8 supply max=20mA up circuits and level shift circuit.
  • Page 25 Smart LTE Module Series SC650T Hardware Design used. If unused, keep this pin open. Power supply for DVDD of rear cameras. 1.1V output power Vnorm=1.1V Add a 1.0uF~2.2uF LDO2_1P1 supply max=1200mA bypass capacitor if used. If unused, keep this pin open.
  • Page 26 Smart LTE Module Series SC650T Hardware Design Microphone bias Dias voltage for MIC_BIAS1 =1.6V~2.85V voltage DMIC1 Microphone bias Dias voltage for MIC_BIAS2 =1.6V~2.85V voltage AMIC2 Microphone bias Dias voltage for MIC_BIAS3 =1.6V~2.85V voltage DMIC2 LINE_OUT_3 Audio output LINE_OUT_R Audio output...
  • Page 27 Smart LTE Module Series SC650T Hardware Design Headset insertion HS_DET Pulled up internally. detection USB Interface Pin Name Pin No. Description Comment Characteristics Charging power input. Vmax=10V Power supply output USB_VBUS 41，42 PI/PO Vmin=4V for OTG device. Vnorm=5.0V USB/charger insertion detection.
  • Page 28 Smart LTE Module Series SC650T Hardware Design through software configuration. max=0.4V (U)SIM1 card reset USIM1_RST min= signal 0.8 × USIM1_VDD max=0.4V (U)SIM1 card clock USIM1_CLK min= signal 0.8 × USIM1_VDD max= 0.2 × USIM1_VDD min= (U)SIM1 card data USIM1_DATA 0.7 × USIM1_VDD signal max=0.4V...
  • Page 29 Smart LTE Module Series SC650T Hardware Design 0.8 × USIM2_VDD 1.8V (U)SIM： Vmax=1.85V Vmin=1.75V Either 1.8V or 2.95V (U)SIM2 card power USIM2_VDD (U)SIM card is supply 2.95V (U)SIM： supported. Vmax=3.1V Vmin=2.8V UART Interface Pin Name Pin No. Description Comment Characteristics UART2 transmit data.
  • Page 30 Smart LTE Module Series SC650T Hardware Design 2.95V SD card： max=0.37V min=2.2V 1.8V SD card： max=0.58V min=1.27V max=0.45V min=1.4V Command signal of SD_CMD SD card 2.95V SD card： max=0.73V min=1.84V max=0.37V min=2.2V 1.8V SD card： SD_DATA0 max=0.58V min=1.27V SD_DATA1 max=0.45V...
  • Page 31 Smart LTE Module Series SC650T Hardware Design TP0_I2C_ I2C data signal of 1.8V power domain. touch panel (TP0) Reset signal of max=0.45V 1.8V power domain. TP1_RST touch panel (TP1) min=1.35V Active low. Interrupt signal of max=0.63V TP1_INT 1.8V power domain.
  • Page 32 Smart LTE Module Series SC650T Hardware Design LCD0 MIPI lane 1 DSI0_LN1_P data signal (positive) LCD0 MIPI lane 2 DSI0_LN2_N data signal (negative) LCD0 MIPI lane 2 DSI0_LN2_P data signal (positive) LCD0 MIPI lane 3 DSI0_LN3_N data signal (negative) LCD0 MIPI lane 3...
  • Page 33 Smart LTE Module Series SC650T Hardware Design Camera Interfaces Pin Name Pin No. Description Comment Characteristics MIPI clock signal of CSI0_CLK_N rear camera (negative) MIPI clock signal of CSI0_CLK_P rear camera (positive) MIPI lane 0 data CSI0_LN0_N signal of rear...
  • Page 34 Smart LTE Module Series SC650T Hardware Design MIPI lane 0 data CSI2_LN0_P signal of front camera (positive) MIPI lane 1 data CSI2_LN1_N signal of front camera (negative) MIPI lane 1 data CSI2_LN1_P signal of front camera (positive) MIPI lane 2 data...
  • Page 35 Smart LTE Module Series SC650T Hardware Design depth camera min=1.35V DCAM_ Power down signal max=0.45V PWDN of depth camera min=1.35V DCAM_I2C_ I2C data signal of 1.8V power domain. depth camera DCAM_I2C_ I2C clock signal of 1.8V power domain. depth camera...
  • Page 36 Smart LTE Module Series SC650T Hardware Design open. Charging Interface Pin Name Pin No. Description Comment Characteristics Differential input signal of battery BAT_PLUS Must be connected. voltage detection (plus) Differential input signal of battery BAT_MINUS Must be connected. voltage detection...
  • Page 37 Smart LTE Module Series SC650T Hardware Design max=0.45V GPIO_36 GPIO min=1.4V Suggest as GPIO_42 GPIO ACCL_INT Suggest as GPIO_43 GPIO ALSP_INT GPIO_44 GPIO Suggest as MAG_INT Suggest as GPIO_45 GPIO GYRO_INT GPIO_46 GPIO GPIO_48 GPIO GPIO_59 GPIO GPIO_60 GPIO GPIO_90...
  • Page 38 Smart LTE Module Series SC650T Hardware Design I2S Interface Pin Name Pin No. Description Comment Characteristics Master clock signal I2S_MCLK of I2S interface Clock signal of I2S I2S_1_SCK interface Channel selection I2S_1_WS signal of I2S interface Data0 signal of I2S...
  • Page 39 Smart LTE Module Series SC650T Hardware Design Flash/torch current FLASH_LED1 driver output Support flash and torch modes. Flash/torch current FLASH_LED2 driver output Emergency Download Interface Pin Name Pin No. Description Comment Characteristics Pulled up to Force the module to LDO5_1P8 during...

  • Page 40: Power Supply

    Smart LTE Module Series SC650T Hardware Design 164,165,16 Keep these pins RESERVED 6,190,191, Reserved pins open. 192，222 3.4. Power Supply 3.4.1. Power Supply Pins SC650T provides 3 VBAT pins,2 VDD_RF pins and 2 VPH_PWR pins. VBAT pins are dedicated for connection with an external power supply.

  • Page 41: Reference Design For Power Supply

    Smart LTE Module Series SC650T Hardware Design the structure of the power supply. VBAT VDD_RF VBAT 100nF 33pF 10pF 100nF 33pF 10pF 100uF Module Figure 3: Star Structure of Power Supply 3.4.3. Reference Design for Power Supply The power design for the module is very important, as the performance of module largely depends on the power source.

  • Page 42: Turn On And Off Scenarios

    Smart LTE Module Series SC650T Hardware Design NOTES It is recommended to switch off the power supply for module in abnormal state, and then switch on the power to restart the module. The module supports battery charging function by default. If the above power supply design is adopted, please make sure the charging function is disabled by software, or connect VBAT to Schottky diode in series to avoid the reverse current to the power supply chip.
  • Page 43 Smart LTE Module Series SC650T Hardware Design Figure 6: Turn on the Module Using Keystroke The turning on scenario is illustrated in the following figure. Note2 VBA T (Typ e:3.8V) PWRKEY >1.6s 61.2ms LDO5_1P8 Software controlled Software LDO6_1P8 controlled LDO10_2P8...

  • Page 44: Turn Off Module

    Smart LTE Module Series SC650T Hardware Design The turn-on timing might be different from the above figure when the module powers on for the first time. Make sure that VBAT is stable before pulling down PWRKEY pin. The recommended time between them is no less than 30ms.

  • Page 45: Power Output

    Smart LTE Module Series SC650T Hardware Design If RTC is ineffective, it can be synchronized through network after the module is powered on.  2.0V~3.25V input voltage range and 3.0V typical value for VRTC, when VBAT is disconnected.  When powered by VBAT, the RTC error is 50ppm. When powered by VRTC, the RTC error is about 200ppm.

  • Page 46: Battery Charge And Management

    Smart LTE Module Series SC650T Hardware Design 3.8. Battery Charge and Management SC650T module supports a fully programmable switch-mode Li-ion battery charge function. It can charge single-cell Li-ion and Li-polymer battery. The battery charger of SC650T module supports trickle charging, pre-charge, constant current charging and constant voltage charging modes, which optimize the charging procedure for Li-ion batteries.
  • Page 47 Smart LTE Module Series SC650T Hardware Design thermistor (47K 1% NTC thermistor with B-constant of 4050K by default; SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to VBAT_THERM pin. If VBAT_THERM pin is not connected, there will be malfunctions such as boot error, battery charging failure, battery level display error, etc.

  • Page 48: Usb Interface

    Smart LTE Module Series SC650T Hardware Design 3.9. USB Interface SC650T provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0/2.0 specifications and supports super speed (5Gbps) on USB 3.0, high speed (480Mbps) on USB 2.0 and full speed (12Mbps) modes.
  • Page 49 Smart LTE Module Series SC650T Hardware Design the OTG device is attached: when USB_ID is kept open (high level by default), SC650T is in USB slave mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply power for peripherals with maximum output of 5V/1A.

  • Page 50: Uart Interfaces

    Smart LTE Module Series SC650T Hardware Design important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides.  Keep the ESD protection devices as close as possible to the USB connector.
  • Page 51 Smart LTE Module Series SC650T Hardware Design UART4_TXD UART4 transmit data UART4_RXD UART4 receive data UART5_RXD UART5 receive data UART5_TXD UART5 transmit data UART5_CTS UART5 clear to send UART5_RTS UART5 request to send UART6_RXD UART6 receive data UART6_TXD UART6 transmit data UART5 is a 4-wire UART interface with 1.8V power domain.

  • Page 52: U)Sim Interfaces

    Smart LTE Module Series SC650T Hardware Design 1.8V 3.3V VCCA VCCB TXD_3.3V UART5_TXD TXD_1.8V DIN 1 DOUT1 RTS_3.3V UART5_RTS RTS_1.8V DIN 2 DOUT2 DIN 3 DOUT3 DIN 4 DOUT4 DIN 5 DOUT5 R1OUTB RXD_1.8V UART5_RXD RXD _3.3V ROUT1 RIN1 ROUT 2...
  • Page 53 Smart LTE Module Series SC650T Hardware Design Pull up to USIM1_VDD with a 10K USIM1_DATA (U)SIM1 card data signal resistor. Either 1.8V or 2.95V (U)SIM card USIM1_VDD (U)SIM1 card power supply is supported. Active low. Need external pull-up to 1.8V.

  • Page 54: Sd Card Interface

    Smart LTE Module Series SC650T Hardware Design USIM _VDD (U)SIM Card Connector 100nF USIM_ VDD USIM_ RST USIM_ CLK Module USIM_ DET USIM_ DATA 22pF 22pF 22pF Figure 16: Reference Circuit for (U)SIM Interface with a 6-pin (U)SIM Card Connector...
  • Page 55 Smart LTE Module Series SC650T Hardware Design Table 12: Pin Definition of SD Card Interface Pin Name Pin No. Description Comment Vnorm=2.95V SD_LDO11 Power supply for SD card max=800mA SD card pull-up power Support 1.8V or 2.95V power supply. SD_LDO12 supply The maximum drive current is 50mA.

  • Page 56: Gpio Interfaces

    Smart LTE Module Series SC650T Hardware Design CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please control the characteristic impedance of them as 50Ω, and do not cross them with other traces. It is recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD, DATA0, DATA1, DATA2 and DATA3.
  • Page 57 Smart LTE Module Series SC650T Hardware Design UART2_TXD GPIO_4 B-PD:nppukp UART2_RXD GPIO_5 B-PD:nppukp Wakeup TP1_I2C_SDA GPIO_6 B-PD:nppukp TP1_I2C_SCL GPIO_7 B-PD:nppukp TP1_RST GPIO_8 B-PD:nppukp TP1_INT GPIO_9 B-PD:nppukp Wakeup TP0_I2C_SDA GPIO_10 B-PD:nppukp TP0_I2C_SCL GPIO_11 B-PD:nppukp UART4_TXD GPIO_12 B-PD:nppukp Wakeup UART4_RXD GPIO_13 B-PD:nppukp...
  • Page 58 Smart LTE Module Series SC650T Hardware Design CAM_I2C_SDA GPIO_29 B-PD:nppukp CAM_I2C_SCL GPIO_30 B-PD:nppukp DCAM_I2C_SDA GPIO_31 B-PD:nppukp Wakeup DCAM_I2C_SCL GPIO_32 B-PD:nppukp GPIO_33 GPIO_33 B-PD:nppukp GPIO_36 GPIO_36 B-PD:nppukp Wakeup MCAM_PWDN GPIO_39 B-PD:nppukp MCAM_RST GPIO_40 B-PD:nppukp GPIO_42 GPIO_42 B-PD:nppukp Wakeup GPIO_43 GPIO_43 B-PD:nppukp...
  • Page 59 Smart LTE Module Series SC650T Hardware Design I2S_1_SCK GPIO_91 B-PD:nppukp Wakeup I2S_1_WS GPIO_92 B-PD:nppukp I2S_1_D0 GPIO_93 B-PD:nppukp Wakeup I2S_1_D2 GPIO_94 B-PD:nppukp I2S_1_D3 GPIO_95 B-PD:nppukp WSA_EN GPIO_96 B-PD:nppukp GPIO_97 GPIO_97 B-PD:nppukp Wakeup GPIO_98 GPIO_98 B-PD:nppukp GPIO_99 GPIO_99 B-PD:nppukp GRFC is only...

  • Page 60: I2C Interfaces

    Smart LTE Module Series SC650T Hardware Design More details about GPIO configuration, please refer to document [2]. 3.14. I2C Interfaces SC650T provides five I2C interfaces. As an open drain output, each I2C interface should be pulled up to 1.8V voltage. The SENSOR_I2C interface supports only sensors of the aDSP architecture.

  • Page 61: Spi Interfaces

    Smart LTE Module Series SC650T Hardware Design Table 16: Pin Definition of I2S Interface Pin Name Pin No Description Comment Master clock signal of I2S_MCLK I2S_MCLK I2S interface Clock signal of I2S I2S_1_SCK I2S_1_SCK interface Channel selection signal I2S_1_WS I2S_1_WS...

  • Page 62: Adc Interfaces

    Smart LTE Module Series SC650T Hardware Design multiplexed into I2S FP_SPI_CLK Clock signal of SPI interface interface. FP_SPI_MOSI Master out slave in of SPI interface FP_SPI_MISO Master in salve out of SPI interface 3.17. ADC Interfaces SC650T provides two analog-to-digital converter (ADC) interfaces, and the pin definition is shown below.

  • Page 63: Lcm Interfaces

    Smart LTE Module Series SC650T Hardware Design VIB_DRV VIB_DRV Module Motor 33pF PESD5V0H1BSF Figure 18: Reference Circuit for Vibrator Connection 3.19. LCM Interfaces SC650T module provides two LCM interfaces, and supports dual LCDs with WUXGA (1900×1200) display. The interfaces support high speed differential data transmission, with up to eight lanes.
  • Page 64 Smart LTE Module Series SC650T Hardware Design LCD0 MIPI clock signal DSI0_CLK_N (negative) LCD0 MIPI clock signal DSI0_CLK_P (positive) LCD0 MIPI lane 0 data signal DSI0_LN0_N (negative) LCD0 MIPI lane 0 data signal DSI0_LN0_P (positive) LCD0 MIPI lane 1 data signal...
  • Page 65 Smart LTE Module Series SC650T Hardware Design LDO 6_1P8 LCD_BIAS_P LCD_BIAS_P LCD_BIAS_N LCD_BIAS_N LPTE LCD0_TE RESET LCD0_ RST LCD_ID PMU_MPP2 NC (SDA-TP) NC (SCL-TP) NC (RST-TP) NC (EINT-TP) VIO18 VCC28 NC (VTP-TP) DSI0_LN3_P MIPI_TDP3 DSI0_LN3_N MIPI_TDN3 DSI0_LN2_P MIPI_TDP2 MIPI_TDN2 DSI0_LN2_N...
  • Page 66 Smart LTE Module Series SC650T Hardware Design LDO6_1P8 LEDA LCD_BIAS_P LEDK LCD_BIAS_N LPTE LCD1_TE RESET LCD1_RST LCD_ID NC (SDA-TP) NC (SCL-TP) NC (RST-TP) 1 uF NC (EINT-TP) VIO18 VCC28 NC (VTP-TP) DSI1_LN3_P MIPI_TDP3 MIPI_TDN3 DSI1_LN3_N DSI1_LN2_P MIPI_TDP2 MIPI_TDN2 DSI1_LN2_N DSI1_LN1_P...

  • Page 67: Touch Panel Interfaces

    Smart LTE Module Series SC650T Hardware Design 3.20. Touch Panel Interfaces SC650T provides two I2C interfaces for connection with Touch Panel (TP), and also provides the corresponding power supply and interrupt pins. The pin definition of touch panel interfaces is illustrated below.

  • Page 68: Camera Interfaces

    Smart LTE Module Series SC650T Hardware Design LDO 6_1P8 LDO10_2P8 2.2K 2.2K SDA 1.8V TP_I2C_SDA TP_I2C_SCL SCL 1.8V TP_RST RESET 1.8V INT 1.8V TP_INT VDD 2.8V 4.7uF 100nF Module Figure 22: Reference Circuit Design for Touch Panel Interfaces NOTE TP is powered by LDO10_2P8 by default and LDO10_2P8 can output 150mA current. It is recommended to use an external LDO power supply if dual-TP or other applications need to be supported.
  • Page 69 Smart LTE Module Series SC650T Hardware Design for digital core circuit of max=600mA front camera MIPI clock signal of rear CSI0_CLK_N camera (negative) MIPI clock signal of rear CSI0_CLK_P camera (positive) MIPI lane 0 data signal of CSI0_LN0_N rear camera (negative)
  • Page 70 Smart LTE Module Series SC650T Hardware Design Master clock signal of rear MCAM_MCLK camera Master clock signal of front SCAM_MCLK camera Reset signal of rear MCAM_RST camera Power down signal of rear MCAM_PWDN camera Reset signal of front SCAM_RST camera...
  • Page 71 Smart LTE Module Series SC650T Hardware Design The following is a reference circuit design for two-camera applications. AF_VDD LDO17_2P85 AVDD LDO22_2P8 DVDD LDO2_1P1 DOVDD MCAM_ RST LDO 6_1P8 MCAM_PWDN 2.2K 2.2K MCAM_MCLK CAM_I2C_ SDA CAM_I2C_ SCL CSI0_LN3_P CSI0_LN3_N CSI0_LN2_P CSI0_LN2_N...

  • Page 72: Design Considerations

    Smart LTE Module Series SC650T Hardware Design CSI0 is used for rear camera, and CSI2 is used for front camera. 3.21.1. 3.21.1. Design Considerations  Special attention should be paid to the pin definition of LCM/camera connectors. Assure the SC650T and the connectors are correctly connected.
  • Page 73 Smart LTE Module Series SC650T Hardware Design DSI1_CLK_N 11.69 0.02 DSI1_CLK_P 11.71 DSI1_LN0_N 11.46 0.09 DSI1_LN0_P 11.56 DSI1_LN1_N 15.26 0.01 DSI1_LN1_P 15.27 DSI1_LN2_N 15.12 -0.65 DSI1_LN2_P 14.47 DSI1_LN3_N 16.15 -0.01 DSI1_LN3_P 16.14 CSI0_CLK_N 17.80 0.06 CSI0_CLK_P 17.86 CSI0_LN0_N 17.73 -0.01 CSI0_LN0_P 17.73...

  • Page 74: Flashlight Interfaces

    Smart LTE Module Series SC650T Hardware Design CSI2_LN2_N 22.96 -0.01 CSI2_LN2_P 22.95 CSI2_LN3_N 22.77 -0.36 CSI2_LN3_P 22.41 3.21.2. Flashlight Interfaces SC650T module supports 2 flash LED drivers, with maximal output current up to 1.5A in flash mode and 300mA in torch mode. The default output current is 1A in flash mode and 300mA in torch mode.

  • Page 75: Sensor Interfaces

    Smart LTE Module Series SC650T Hardware Design 3.22. Sensor Interfaces SC650T module supports communication with sensors via I2C interface, and it supports various sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor. Table 25: Pin Definition of Sensor Interfaces Pin Name Pin No.
  • Page 76 Smart LTE Module Series SC650T Hardware Design Dias voltage for MIC_BIAS3 Microphone bias voltage DMIC2 LINE_OUT_3 Audio output LINE_OUT_REF Audio output reference ground LINE_OUT_4 Audio output Analog microphone positive AMIC1_P input for channel 1 Analog microphone negative AMIC1_M input for channel 1...

  • Page 77: Reference Circuit Design For Microphone Interfaces

    Smart LTE Module Series SC650T Hardware Design 3.23.1. Reference Circuit Design for Microphone Interfaces Figure 25: Reference Circuit Design for Analog ECM-type Microphone 100nF MIC_BIASn AMICx_M AMICx_P Figure 26: Reference Circuit Design for MEMS-type Microphone SC650T_Hardware_Design 76 / 131...

  • Page 78: Reference Circuit Design For Earpiece Interface

    Smart LTE Module Series SC650T Hardware Design MIC _ BIAS Digital MIC DMIC_CLK DMIC_CLK DMIC_DATA DMIC_DATA 100nF 10uF Module Figure 27:Reference Circuit Design for Digital Microphone 3.23.2. Reference Circuit Design for Earpiece Interface Figure 28: Reference Circuit Design for Earpiece Interface...

  • Page 79: Reference Circuit Design For Headphone Interface

    Smart LTE Module Series SC650T Hardware Design 3.23.3. Reference Circuit Design for Headphone Interface MIC_BIAS2 100pF 33pF 33pF AMIC2_M AMIC2_P HPH_L HS_DET HPH_R HPH_REF D1 D2 D3 D4 680pF 680pF Figure 29: Reference Circuit Design for Headphone Interface 3.23.4. Reference Circuit Design for Loudspeaker Interface...

  • Page 80: Emergency Download Interface

    Smart LTE Module Series SC650T Hardware Design that the resonant frequency point of a capacitor largely depends on the material and production technique. Therefore, customers would have to discuss with their capacitor vendors to choose the most suitable capacitor for filtering out high-frequency noises.
  • Page 81 Smart LTE Module Series SC650T Hardware Design Table 27: Pin Definition of LED Driver Interfaces Pin Name Pin No. Description Comment The output current does not LED_RED Red LED light exceed 12mA The output current does not LED_GRN Green LED light...

  • Page 82: Wi-Fi And Bt

    Smart LTE Module Series SC650T Hardware Design Wi-Fi and BT SC650T module provides a shared antenna interface ANT_WIFI/BT for Wi-Fi and Bluetooth (BT) functions. The interface impedance is 50Ω. External antennas such as PCB antenna, sucker antenna and ceramic antenna can be connected to the module via the interface, so as to achieve Wi-Fi and BT functions.
  • Page 83 Smart LTE Module Series SC650T Hardware Design 802.11g 54Mbps 14dBm±2.5dB 802.11n HT20 MCS0 15dBm±2.5dB 13dBm±2.5dB 802.11n HT20 MCS7 802.11n HT40 MCS0 15dBm±2.5dB 13dBm±2.5dB 802.11n HT40 MCS7 802.11a 6Mbps 17dBm± 2.5dB 16dBm± 2.5dB 802.11a 54Mbps 802.11n HT20 MCS0 17dBm±2.5dB 16dBm± 2.5dB 802.11n HT20...

  • Page 84: Bt Overview

    Smart LTE Module Series SC650T Hardware Design 802.11n HT20 MCS7 -72dBm 802.11n HT40 MCS0 -89dBm 802.11n HT40 MCS7 -70dBm 802.11a 6Mbps -92dBm 802.11a 54Mbps -74dBm 802.11n HT20 MCS0 -91dBm 802.11n HT20 MCS7 -73dBm 5GHz 802.11n HT40 MCS0 -88dBm 802.11n HT40...

  • Page 85: Bt Performance

    Smart LTE Module Series SC650T Hardware Design Table 30: BT Data Rate and Versions Version Data rate Maximum Application Throughput Comment 1Mbit/s > 80Kbit/s 2.0+EDR 3Mbit/s > 80Kbit/s 3.0+HS 24Mbit/s Reference to 3.0+HS 24Mbit/s Reference to 4.0 LE Reference specifications are listed below: ...

  • Page 86: Gnss

    Smart LTE Module Series SC650T Hardware Design GNSS SC650T module integrates a Qualcomm IZat™ GNSS engine (Gen 8C) which supports multiple positioning and navigation systems including GPS, GLONASS and BeiDou. With an embedded LNA, the module provides greatly improved positioning accuracy.

  • Page 87: Gnss Rf Design Guidelines

    Smart LTE Module Series SC650T Hardware Design 5.2. GNSS RF Design Guidelines Bad design of antenna and layout may cause reduced GNSS receiving sensitivity, longer GNSS positioning time, or reduced positioning accuracy. In order to avoid these, please follow the design rules listed below: ...

  • Page 88: Antenna Interfaces

    Smart LTE Module Series SC650T Hardware Design Antenna Interfaces SC650T provides four antenna interfaces for main antenna, Rx-diversity/MIMO antenna, GNSS antenna, and Wi-Fi/BT antenna, respectively. The antenna ports have an impedance of 50Ω. 6.1. Main/Rx-diversity Antenna Interfaces The pin definition of main/Rx-diversity antenna interfaces is shown below.

  • Page 89: Main And Rx-Diversity Antenna Interfaces Reference Design

    Smart LTE Module Series SC650T Hardware Design LTE-FDD B25 1930~1995 1850~1915 LTE-FDD B26 859~894 814~849 LTE-FDD B66 2110~2200 1710~1780 Table 35: SC650T-EM Module Operating Frequencies 3GPP Band Receive Transmit Unit LTE-FDD B1 2110~2170 1920~1980 LTE-FDD B3 1805~1880 1710~1785 LTE-FDD B7...

  • Page 90: Reference Design Of Rf Layout

    Smart LTE Module Series SC650T Hardware Design Figure 33: Reference Circuit Design for Main and Rx-diversity Antenna Interfaces 6.1.2. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’...
  • Page 91 Smart LTE Module Series SC650T Hardware Design Figure 36: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 37: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: ...

  • Page 92: Wi-Fi/Bt Antenna Interface

    Smart LTE Module Series SC650T Hardware Design 6.2. Wi-Fi/BT Antenna Interface Table 36: Pin Definition of Wi-Fi/BT Antenna Interface Pin Name Pin No. Description Comment ANT_WIFI/BT Wi-Fi/BT antenna interface 50Ω impedance Table 37: Wi-Fi/BT Frequency Type Frequency Unit 2402~2482 802.11a/b/g/n/ac 5180~5825 BT4.2 LE...

  • Page 93: Recommended Circuit For Passive Antenna

    Smart LTE Module Series SC650T Hardware Design Table 38: Pin Definition of GNSS Antenna Pin Name Pin No. Description Comment ANT_GNSS GNSS antenna Interface 50Ω impedance For test purpose only. GNSS_LNA_EN LNA enable control If unused, keep it open. Table 39: GNSS Frequency...

  • Page 94: Antenna Installation

    Smart LTE Module Series SC650T Hardware Design still requires stable and clean power supplies. It is recommended to use high performance LDO as the power supply. A reference design of GNSS active antenna is shown below. Active Antenna 100pF 56nH...

  • Page 95: Recommended Rf Connector For Antenna Installation

    Smart LTE Module Series SC650T Hardware Design Frequency range: 1559MHz~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive Antenna Gain: > 0dBi GNSS Active Antenna Noise Figure: < 1.5dB (Typ.) Active Antenna Gain: > -2dBi Active Antenna Embedded LNA Gain: < 17dB (Typ.) Active Antenna Total Gain: <...
  • Page 96 Smart LTE Module Series SC650T Hardware Design Figure 42: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 43: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com. SC650T_Hardware_Design 95 / 131...

  • Page 97: Electrical, Reliability And Radio Characteristics

    Smart LTE Module Series SC650T Hardware Design Electrical, Reliability and Radio Characteristics 7.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 41: Absolute Maximum Ratings...

  • Page 98: Operation And Storage Temperatures

    Smart LTE Module Series SC650T Hardware Design Parameter Description Conditions Typ. Unit battery. 7.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 43: Operation and Storage Temperatures Parameter Typ. Unit Operating temperature range °...
  • Page 99 Smart LTE Module Series SC650T Hardware Design Table 44: SC650T-NA Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down Sleep (USB disconnected) @DRX=6 LTE-FDD supply Sleep (USB disconnected) current @DRX=8 Sleep (USB disconnected) @DRX=9 LTE-FDD B2 @max power...

  • Page 100: Rf Output Power

    Smart LTE Module Series SC650T Hardware Design LTE-FDD B3 @max power LTE-FDD B7 @max power LTE-FDD B20 @max power LTE-TDD B28 @max power 7.5. 7.5. RF Output Power The following table shows the RF output power of SC650T module. Table 46: SC650T-NA RF Output Power...

  • Page 101: Rf Receiving Sensitivity

    Smart LTE Module Series SC650T Hardware Design LTE-FDD B7 23dBm± 2dB <-39dBm LTE-FDD B20 23dBm± 2dB <-39dBm LTE-FDD B28 23dBm± 2dB <-39dBm 7.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of SC650T module. Table 48: SC650T-NA RF Receiving Sensitivity x` Receive Sensitivity (Typ.)

  • Page 102: Electrostatic Discharge

    Smart LTE Module Series SC650T Hardware Design LTE-FDD B1 (10M) -99.1dBm -99dBm -102.3dBm -96.3dBm LTE-FDD B3 (10M) -98.9dBm -99.5dBm -102.1dBm -93.3dBm LTE-FDD B7 (10M) -98.5dBm -98.8dBm -101.9dBm -94.3dBm LTE-FDD B20 (10M) -99.7dBm -99.6dBm -102.4dBm -93.3dBm LTE-TDD B28 (10M) -99.8dBm -99.4dBm -102.2dBm...

  • Page 103: Mechanical Dimensions

    Smart LTE Module Series SC650T Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the tolerances for dimensions without tolerance values are ± 0.05mm. 8.1. Mechanical Dimensions of the Module...
  • Page 104 Smart LTE Module Series SC650T Hardware Design Figure 45: Module Bottom Dimensions (Top View) SC650T_Hardware_Design 103 / 131...

  • Page 105: Recommended Footprint

    Smart LTE Module Series SC650T Hardware Design 8.2. Recommended Footprint Figure 46: Recommended Footprint (Top View) NOTES For easy maintenance of the module, keep about 3mm between the module and other components on host PCB. All RESERVED pins should be kept open and MUST NOT be connected to ground.

  • Page 106: Top And Bottom View Of The Module

    Figure 47: Top View of the Module Figure 48: Bottom View of the Module NOTE These are renderings of SC650T module. For authentic dimension and appearance, please refer to the module that you receive from Quectel. SC650T_Hardware_Design 105 / 131...

  • Page 107: Storage, Manufacturing And Packaging

    Smart LTE Module Series SC650T Hardware Design Storage, Manufacturing and Packaging 9.1. Storage SC650T is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40º C/90%RH.

  • Page 108: Manufacturing And Soldering

    Smart LTE Module Series SC650T Hardware Design 9.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass.

  • Page 109: Packaging

    Smart LTE Module Series SC650T Hardware Design Reflow Zone Max slope 2 to 3° C/sec Reflow time (D: over 220° C) 40 to 60 sec Max temperature 240° C ~ 245° C Cooling down slope 1 to 4° C/sec Reflow Cycle Max reflow cycle 9.3.
  • Page 110 Smart LTE Module Series SC650T Hardware Design Figure 51: Reel Dimensions Table 52: Reel Packaging Model Name MOQ for MP Minimum Package: 200pcs Minimum Package×4=800pcs Size: 398mm × 383mm × 83mm Size: 420mm × 350mm × 405mm SC650T N.W: 1.92kg N.W: 8.18kg...

  • Page 111: Appendix A References

    Smart LTE Module Series SC650T Hardware Design Appendix A References Table 53: Related Documents Document Name Remark Quectel_Smart_EVB-G2_User_Guide EVB User Guide for SC650T Quectel_SC650T_GPIO_Configuration GPIO Configuration of SC650T Quectel_RF_Layout_Application_Note RF Layout Application Note Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Quectel_SC650T_Reference_Design...
  • Page 112 Smart LTE Module Series SC650T Hardware Design Global Positioning System Graphics Processing Unit Half Rate HSDPA High Speed Down Link Packet Access HSPA High Speed Packet Access Input/Output Inphase and Quadrature Liquid Crystal Display LCD Module Light Emitting Diode Low Noise Amplifier...
  • Page 113 Smart LTE Module Series SC650T Hardware Design Short Message Service Terminal Equipment Transmitting Direction UART Universal Asynchronous Receiver & Transmitter UMTS Universal Mobile Telecommunications System (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value...

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