Usb0 Type-C - Quectel SG865W Series Hardware Design

4.1.1. USB0 Type-C

Module
USB_VBUS
USB0_DP
USB0_DM
USB_CC1
USB_CC2
USB_SBU1
USB_SBU2
USB0 _ SS0 _RX_P
_ SS0 _RX_M
USB0
_ SS0 _TX_P
USB0
_ SS0 _TX_M
USB0
_ SS1 _RX_P
USB0
_ SS1 _RX_M
USB0
_ SS1 _TX_P
USB0
_
USB0 SS1
_TX_M
Follow the following principles while designing the USB interfaces to ensure USB performance.
⚫
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90 Ω.
⚫
Pay attention to the influence of junction capacitance of ESD protection components on USB data
traces. Typically, the junction capacitance value should be less than 2 pF for USB 2.0 and less than
0.5 pF for USB 3.1.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices, and RF signal traces. It is
important to route the USB differential traces in inner-layer and surround the traces with ground on
that layer and with ground planes above and below.
⚫
For USB 2.0, the total trace length of each signal should be less than 250 mm, and the length
matching of each differential pair should be less than 2 mm.
⚫
For USB 3.1, intra-pair length matching (USB_SS_TX/RX_P/M) should be less than 0.7 mm, while
the inter-pair length matching (USB_SS_Tx/Rx) should be less than 10 mm.
⚫
For DisplayPort, intra-pair length matching (DP_AUX_P/M) should be less than 7 mm.
Table 12: USB Trace Length Inside the Module
Signal
USB0_DP
USB0_DM
USB0_SS0_RX_P
SG865W_Series_Hardware_Design
Figure 14: USB Type-C Interface Reference Design
Pin No.
442
436
412
C1
C2
C3
C4
C5
C6
C7
C8
Length (mm)
53.00
53.16
18.33
Smart Module Series
USB Type-C
VBUS
D+
D-
CC1
CC2
SBU1
SBU2
RX1+
RX1-
TX1+
TX1-
RX2+
RX2-
TX2+
TX2-
Length Difference (mm)
-0.16
-0.30
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